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检索条件"任意字段=Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization"

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proceedings of the 2008 CGO - Sixth international symposium on code generation and optimization

Proceedings of the 2008 CGO - Sixth International Symposium ...

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6th international symposium on code generation and optimization, CGO 2008

ISBN: (纸本)9781595939784

The proceedings contain 24 papers. The topics discussed include: code optimization of parallel programs: evolutionary vs. revolutionary approaches;issues and challenges in compiling for graphics processors;parallelism by design: data analysis with Sawzall;automatic array inlining in Java virtual machines;phase-based adaptive recompilation in an JVM;fast liveness checking for SSA-form programs;near-optimal instruction selection on DAGs;comprehensive path-sensitive data-flow analysis;accurate critical path prediction via random trace construction;efficient fine-grained binary instrumentation with applications to taint-tracking;prediction and trace compression of data access addresses through nested loop recognition;latency-tolerant software pipelining in a production compiler;parallel-stage decoupled software pipelining;and modulo scheduling for highly customized datapaths to increase hardware reusability.

关键词： Program compilers

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proceedings of the 2010 CGO - The 8th international symposium on code generation and optimization

Proceedings of the 2010 CGO - The 8th International Symposiu...

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8th international symposium on code generation and optimization, CGO 2010

ISBN: (纸本)9781605586359

The proceedings contain 29 papers. The topics discussed include: a framework for deterministic replay and reproducible analysis of parallel programs;TAO: two-level atomicity for dynamic binary optimizations;large program trace analysis and compression with ZDDs;taming hardware event samples for FDO compilation;lightweight feedback-directed cross-module optimization;automated just-in-time compiler tuning;self-adjusting code cache manager to balance start-up time and memory usage;on improving heap memory layout by dynamic pool allocation;an efficient software transactional memory using commit-time invalidation;efficient compilation of fine-grained SPMD-threaded programs for multicore CPUs;there are at least two sides to every heterogeneous system;decoupled software pipelining creates parallelization opportunities;speculative parallelization of partial reduction variables;and automatic creation of tile size selection models.

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AMOS: Enabling Automatic Mapping for Tensor Computations On Spatial Accelerators with Hardware Abstraction 22

AMOS: Enabling Automatic Mapping for Tensor Computations On ...

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49th ieee/acm annual international symposium on Computer Architecture (ISCA)

作者： Zheng, Size Chen, Renze Wei, Anjiang Jin, Yicheng Han, Qin Lu, Liqiang Wu, Bingyang Li, Xiuhong Yan, Shengen Liang, Yun Peking Univ Beijing Peoples R China Stanford Univ Stanford CA USA Sensetime Res Beijing Peoples R China Shanghai Lab Shanghai Peoples R China

ISBN: (纸本)9781450386104

Hardware specialization is a promising trend to sustain performance growth. Spatial hardware accelerators that employ specialized and hierarchical computation and memory resources have recently shown high performance gains for tensor applications such as deep learning, scientific computing, and data mining. To harness the power of these hardware accelerators, programmers have to use specialized instructions with certain hardware constraints. However, these hardware accelerators and instructions are quite new and there is a lack of understanding of the hardware abstraction, performance optimization space, and automatic methodologies to explore the space. Existing compilers use hand-tuned computation implementations and optimization templates, resulting in sub-optimal performance and heavy development costs. In this paper, we propose AMOS, which is an automatic compilation framework for spatial hardware accelerators. Central to this framework is the hardware abstraction that not only clearly specifies the behavior of spatial hardware instructions, but also formally defines the mapping problem from software to hardware. Based on the abstraction, we develop algorithms and performance models to explore various mappings automatically. Finally, we build a compilation framework that uses the hardware abstraction as compiler intermediate representation (IR), explores both compute mappings and memory mappings, and generates high-performance code for different hardware backends. Our experiments show that AMOS achieves more than 2.50x speedup to hand-optimized libraries on Tensor Core, 1.37x speedup to TVM on vector units of Intel CPU for AVX-512, and up to 25.04x speedup to AutoTVM on dot units of Mali GPU. The source code of AMOS is publicly available.

关键词： spatial accelerators code generation mapping tensor computations

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Auto-generation and auto-tuning of 3D stencil codes on GPU clusters 12

Auto-generation and auto-tuning of 3D stencil codes on GPU c...

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10th international symposium on code generation and optimization, CGO 2012

作者： Zhang, Yongpeng Mueller, Frank North Carolina State University Raleigh NC United States

ISBN: (纸本)9781605586359

This paper develops and evaluates search and optimization techniques for auto-tuning 3D stencil (nearest-neighbor) computations on GPUs. Observations indicate that parameter tuning is necessary for heterogeneous GPUs to achieve optimal performance with respect to a search space. Our proposed framework takes a most concise specification of stencil behavior from the user as a single formula, auto-generates tunable code from it, systematically searches for the best configuration and generates the code with optimal parameter configurations for different GPUs. This auto-tuning approach guarantees adaptive performance for different generations of GPUs while greatly enhancing programmer productivity. Experimental results show that the delivered floating point performance is very close to previous handcrafted work and outperforms other auto-tuned stencil codes by a large margin. Copyright © 2012 acm.

关键词： Graphics processing unit

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Analysis techniques for predicated code

Analysis techniques for predicated code

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29th annual ieee/acm international symposium on Microarchitecture (MICRO-29)

作者： Johnson, R Schlansker, M Hewlett-Packard Lab Palo Alto United States

ISBN: (纸本)0818676418

Predicated execution offers new approaches to exploiting instruction-level parallelism (ILP), but it also presents new challenges for compiler analysis and optimization. In predicated code, each operation is guarded by a boolean operand whose run-time value determines whether the operation is executed or nullified While research has shown the utility of predication in enhancing ILP, there has been little discussion of the difficulties surrounding compiler support for predicated execution Conventional program analysis tools (e.g. data flow analysis) assume that operations execute unconditionally within each basic block and thus make incorrect assumptions about the run-rime behavior of predicated code. These fools can be modified to be correct without requiring predicate analysis, but this yields overly-conservative results in crucial areas such as scheduling and register allocation. To generate high-quality code for machines offering predicated execution, a compiler must incorporate information about relations between predicates into its analysis. We present new techniques far analyzing predicated code. Operations which compute predicates are analyzed to determine relations between predicate values These relations are captured in a graph-based data structure, which supports efficient manipulation of boolean expressions representing facts about predicated code. This approach forms the basis for predicate-sensitive dataflow analysis. Conventional data flow algorithms can be systematically upgraded to be predicate sensitive by incorporating information about predicates. Predicate-sensitive data flow analysis yields significantly more accurate results than conventional data flow analysis when applied to predicated code.

关键词： Program compilers

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Free Launch: Optimizing GPU Dynamic Kernel Launches through Thread Reuse 48

Free Launch: Optimizing GPU Dynamic Kernel Launches through ...

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48th annual ieee/acm international symposium on Microarchitecture (MICRO)

作者： Chen, Guoyang Shen, Xipeng North Carolina State Univ Dept Comp Sci 890 Oval Dr Raleigh NC 27695 USA

ISBN: (纸本)9781450340342

Supporting dynamic parallelism is important for GPU to benefit a broad range of applications. There are currently two fundamental ways for programs to exploit dynamic parallelism on GPU: a software-based approach with software-managed worklists, and a hardware-based approach through dynamic subkernel launches. Neither is satisfactory. The former is complicated to program and is often subject to some load imbalance;the latter suffers large runtime overhead. In this work, we propose free launch, a new software approach to overcoming the shortcomings of both methods. It allows programmers to use subkernel launches to express dynamic parallelism. It employs a novel compiler-based code transformation named subkernel launch removal to replace the subkernel launches with the reuse of parent threads. Coupled with an adaptive task assignment mechanism, the transformation reassigns the tasks in the subkernels to the parent threads with a good load balance. The technique requires no hardware extensions, immediately deployable on existing GPUs. It keeps the programming convenience of the subkernel launch-based approach while avoiding its large runtime overhead. Meanwhile, its superior load balancing makes it outperform manual worklist-based techniques by 3X on average.

关键词： GPU Dynamic Parallelism optimization Thread Reuse Compiler Runtime Adaptation

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Structure layout optimization for multithreaded programs 07

Structure layout optimization for multithreaded programs

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5th international symposium on code generation and optimization

作者： Raman, Easwaran Hundt, Robert Mannarswamy, Sandya Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Hewlett Packard Corp Java Compilers & Tools Lab Palo Alto CA 94303 USA

ISBN: (纸本)9780769527642

Structure layout optimizations seek to improve runtime performance by improving data locality and reuse. The structure layout heuristics for single-threaded benchmarks differ from those for multi-threaded applications running on multiprocessor machines, where the effects of false sharing need to be taken into account. In this paper we propose a technique for structure layout transformations for multi-threaded applications that optimizes both for improved spatial locality and reduced false sharing, simultaneously. We develop a semi-automatic tool that produces actual structure layouts for multi-threaded programs and outputs the key factors contributing to the layout decisions. We apply this tool on the HP-UX kernel and demonstrate the effects of these transformations for a variety of already highly hand-tuned key structures with different set of properties. We show that naive heuristics can result in massive performance degradations on such a highly tuned application, while our technique generally avoids those pitfalls. The improved structures produced by our tool improve performance by up to 3.2% over a highly tuned baseline.

关键词： Optimizing compilers Protocols Computer science Java Program processors Laboratories Runtime Application software Kernel Degradation

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Techniques for compressing program address traces 27

Techniques for compressing program address traces

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27th annual international symposium on Microarchitecture, MICRO 1994

作者： Pleszkun, Andrew R. Department of Electrical and Computer Engineering University of Colorado-Boulder BoulderCO80309-0425 United States

ISBN: (纸本)0897917073

In this paper a technique for generating consistent, reproducible traces with about an order of magnitude better compression than standard general-purpose compression programs is described. With this approach, the trace is read once, an intermediate form is generated and then read as the input to the second pass over the address stream. No program source code is required, and this technique will work on address streams that include OS calls. As a result of the way the address trace is encoded and processed, representing each reference requires only a fraction of a bit, between 0.00114 to 0.878 bits per reference. For example, the roughly 1.6 billion references generated by the xlisp benchmark from the SPEC92 suite can stored using only about 48.6 million bytes. Depending on the benchmarks, more or less bits per references may be needed. © 1994 acm.

关键词： trace generation compression

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Practical structure layout optimization and advice 06

Practical structure layout optimization and advice

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4th international symposium on code generation and optimization

作者： Hundt, Robert Mannarswamy, Sandya Chakrabarti, Dhruva Hewlett Packard Corp Java Compilers & Tools Lab Palo Alto CA 94304 USA

ISBN: (纸本)0769524990

With the delta between processor clock frequency and memory latency ever increasing and with the standard locality improving transformations maturing, compilers increasingly seek to modify an application's data layout to improve spatial and temporal locality and to reduce cache miss and page fault penalties. In this paper we describe a practical implementation of the data layout optimizations Structure Splitting, Structure Peeling, Structure Field Reordering and Dead Field Removal, both for profile and non-profile based compilations. We demonstrate significant performance gains, but find that automatic transformations fail for a relatively high number of record types because of legality violations or profitability constraints. Additionally, we find a class of desirable transformations for which the framework cannot provide satisfying results. To address this issue we complement the automatic transformations with an advisory tool. We reuse the compiler analysis done for automatic transformation and correlate its results with performance data collected during runtime for structure fields, such as data cache misses and latencies. We then use the compiler as a performance analysis and reporting tool and provide insight into how to layout structure types more efficiently.

关键词： Optimizing compilers Delay Runtime Clocks Profitability Performance analysis Java Laboratories Frequency Performance gain

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CGO 2018 - proceedings of the 2018 international symposium on code generation and optimization

CGO 2018 - Proceedings of the 2018 International Symposium o...

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16th international symposium on code generation and optimization, CGO 2018

ISBN: (纸本)9781450356176

The proceedings contain 31 papers. The topics discussed include: analyzing and optimizing task granularity on the JVM;the generalized matrix chain algorithm;conflict-free vectorization of associative irregular applications with recent SIMD architectural advances;biological computation;nAdroid: statically detecting ordering violations in Android applications;synthesizing programs that expose performance bottlenecks;optimal DNN primitive selection with partitioned Boolean quadratic programming;CUDAAdvisor: LLVM-based runtime profiling for modern GPUs;transforming loop chains via macro dataflow graphs;register allocation for Intel processor graphics;SgxElide: enabling enclave code secrecy via self-modification;look-ahead SLP: auto-vectorization in the presence of commutative operations;AutoPA: automatically generating active driver from original passive driver code;poker: permutation-based SIMD execution of intensive tree search by path encoding;SIMD intrinsics on managed language runtimes;and program generation for small-scale linear algebra applications.

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