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检索条件"任意字段=Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization"

共 545 条记录，以下是51-60 订阅

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Incremental Whole Program optimization and Compilation

Incremental Whole Program Optimization and Compilation

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ieee/acm international symposium on code generation and optimization (CGO)

作者： Sathyanathan, Patrick W. He, Wenlei Tzen, Ten H. Microsoft Corp Redmond WA 98052 USA

ISBN: (纸本)9781509049318

Most modern compilers for statically typed high level languages perform whole program optimization and compilation in order to generate highly optimized code. Whole program analysis and optimization has the advantage of providing the compiler with visibility to the entire program. This allows information to be propagated across procedures to improve the quality of the generated code. The main disadvantage of existing systems with this capability however, is that recompiling a program after an edit incurs the cost of reanalyzing and regenerating code for all functions. Compiler throughput is crucial for developers' everyday edit-compile-test cycle as well as build lab's automated rolling build. Improving the throughput of such builds significantly improves developer productivity and lab efficiency. We present a practical and extensible framework for incremental whole program optimization (WPO) and compilation. It uses two program abstractions, namely a dependence graph representing the program entities that the code for each function depends upon, and lattices of data-flow information that affect the code generated. These abstractions are used to minimize the number of functions that must be reanalyzed and recompiled after a program edit. The framework uses a simple and fast checksum technique for detecting edits to functions and variables, and experimental evidence that this technique works well in practice. We also present a novel mechanism for achieving the no code generation diffrequirement in the presence of multi-level inline expansion. The system has been successfully implemented in the state-of-the-art commercial quality Visual C/C++ compiler and achieves up to 7X compilation speedup for typical edits.

关键词： Algorithms Whole Program optimization

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From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality optimization 2019

From Loop Fusion to Kernel Fusion: A Domain-Specific Approac...

引用

17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Qiao, Bo Reiche, Oliver Hannig, Frank Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781728114361

Optimizing data-intensive applications such as image processing for GPU targets with complex memory hierarchies requires to explore the tradeoffs among locality, parallelism, and computation. Loop fusion as one of the classical optimization techniques has been proven effective to improve locality at the function level. Algorithms in image processing are increasing their complexities and generally consist of many kernels in a pipeline. The inter-kernel communications are intensive and exhibit another opportunity for locality improvement at the system level. The scope of this paper is an optimization technique called kernel fusion for data locality improvement. We present a formal description of the problem by defining an objective function for locality optimization. By transforming the fusion problem to a graph partitioning problem, we propose a solution based on the minimum cut technique to search fusible kernels recursively. In addition, we develop an analytic model to quantitatively estimate potential locality improvement by incorporating domain-specific knowledge and architecture details. The proposed technique is implemented in an image processing DSL and source-to-source compiler called Hipacc, and evaluated over six image processing applications on three Nvidia GPUs. A geometric mean speedup of up to 2.52 can be observed in our experiments(1).

关键词： Kernel Image processing Parallel processing optimization Law Registers

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Bungee Jumps: Accelerating Indirect Branches Through HW/SW Co-Design 48

Bungee Jumps: Accelerating Indirect Branches Through HW/SW C...

引用

48th annual ieee/acm international symposium on Microarchitecture (MICRO)

作者： McFarlin, Daniel S. Zilles, Craig Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Illinois Champaign IL USA

ISBN: (纸本)9781450340342

Indirect branches have historically been a challenge for microarchitectures and code generators alike The recent steady increase in indirect branch predictability has translated into continual performance improvements especially for Out-of-Order processors which benefit wore readily from improvements in branch prediction. In contrast;in-order processors which rely on code generators for performance are still challenged by indirect branches;they are a frequent source of issue stalls and the large number of indirect branch targets and unbiased nature of indirect branches complicate the use of traditional branch handling techniques like assert conversion and predication. To address these limitations;we propose an ISA enhancement with associated code transformation and hardware support that collectively enable the current trend of improved indirect branch predictability to be directly leveraged by code-generators for in-orders. By separating the prediction point of an indirect branch from its resolution point;we enable code generators to emit schedules which more readily match those found by the Out-of-Order. Our technique is particularly beneficial to those processors which leverage dynamic binary translation and optimization such as Transmeta's Efficeon and more recently Nvidia's Project Denver. On a set of indirect branch intensive benchmarks from SPEC 2006, 2000 and 95, We achieve a Geomean speedup on a 4-wide of 11%. We further demonstrate speedups of 23% and 14% speedup on PHP and Python benchmarks.

关键词： Generators Out of order Benchmark testing Schedules Prefetching Hardware code generation Benchmark testing prefetching Computer hardware branches dynamos PROCESSOR sequential processor transcoding Speeding Branch-prediction Co-design

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YaskSite: Stencil optimization Techniques Applied to Explicit ODE Methods on Modern Architectures 21

YaskSite: Stencil Optimization Techniques Applied to Explici...

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19th ieee/acm international symposium on code generation and optimization (CGO)

作者： Alappat, Christie L. Seiferth, Johannes Hager, Georg Korch, Matthias Rauber, Thomas Wellein, Gerhard Univ Erlangen Nurnberg Erlangen Germany Univ Bayreuth Bayreuth Germany

ISBN: (纸本)9781728186139

The landscape of multi-core architectures is growing more complex and diverse. Optimal application performance tuning parameters can vary widely across CPUs, and finding them in a possibly multidimensional parameter search space can be time consuming, expensive and potentially infeasible. In this work, we introduce YaskSite, a tool capable of tackling these challenges for stencil computations. YaskSite is built upon Intel's YASK framework. It combines YASK's flexibility to deal with different target architectures with the Execution-Cache-Memory performance model, which enables identifying optimal performance parameters analytically without the need to run the code. Further we show that YaskSite's features can be exploited by external tuning frameworks to reliably select the most efficient kernel(s) for the application at hand. To demonstrate this, we integrate YaskSite into Offsite, an offline tuner for explicit ordinary differential equation methods, and show that the generated performance predictions are reliable and accurate, leading to considerable performance gains at minimal code generation time and autotuning costs on the latest Intel Cascade Lake and AMD Rome CPUs.

关键词： Performance modeling ECM model Stencil optimization YASK Autotuning PIRK methods

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AN5D: Automated Stencil Framework for High-Degree Temporal Blocking on GPUs 2020

AN5D: Automated Stencil Framework for High-Degree Temporal B...

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18th acm/ieee international symposium on code generation and optimization (CGO)

作者： Matsumura, Kazuaki Zohouri, Hamid Reza Wahib, Mohamed Endo, Toshio Matsuoka, Satoshi Barcelona Supercomp Ctr Barcelona Spain Edgecortix Inc Tokyo Japan AIST Tokyo Japan Tokyo Inst Technol Tokyo Japan RIKEN CCS Kobe Hyogo Japan RWBC OIL Tokyo Japan

ISBN: (纸本)9781450370479

Stencil computation is one of the most widely-used compute patterns in high performance computing applications. Spatial and temporal blocking have been proposed to overcome the memory-bound nature of this type of computation by moving memory pressure from external memory to on-chip memory on GPUs. However, correctly implementing those optimizations while considering the complexity of the architecture and memory hierarchy of GPUs to achieve high performance is difficult. We propose AN5D, an automated stencil framework which is capable of automatically transforming and optimizing stencil patterns in a given C source code, and generating corresponding CUDA code. Parameter tuning in our framework is guided by our performance model. Our novel optimization strategy reduces shared memory and register pressure in comparison to existing implementations, allowing performance scaling up to a temporal blocking degree of 10. We achieve the highest performance reported so far for all evaluated stencil benchmarks on the state-of-the-art Tesla V100 GPU.

关键词： Stencil Computation GPU Automatic code generation Temporal Blocking

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code generation from Formal Models for Automatic RTOS Portability 2019

Code Generation from Formal Models for Automatic RTOS Portab...

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17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Gomes, Renata Martins Baunach, Marcel Graz Univ Technol Inst Tech Informat Graz Austria

ISBN: (纸本)9781728114361

Current approaches for portability of real-time operating systems (RTOSs) for embedded systems are largely based on manual coding, which is arduous and error prone. With increasing dependability requirements for cyber physical systems, specially within the Internet of Things (IoT), along with the expected great diversity of hardware platforms, software platforms will only remain competitive in the long run if they guarantee correct operation and easy deployment to every hardware platform. In this scenario, a new approach to the development and portability of RTOSs that guarantees correct implementations for all current and future devices and hardware architectures becomes indispensable. We present a framework for automatic RTOS portability that integrates model-based design and formal methods into dependable embedded software development. We focus specially on modeling the interaction between software and hardware in order to generate low-level code. This enables automatic portability for hardware-related parts of the OS (i.e., context switching, memory management, security aspects, etc,) as well as for on-chip peripheral drivers (i.e., timers, I/O, etc.). With our framework we will be able to prove the consistency of the refinements as well as that the RTOS model fulfills various functional and non-functional requirements. Automatic code generation guarantees that the model is correctly translated to machine language, avoiding implementation mistakes common to manual coding. Changes on the software, for bug fixes or testing of new concepts, for example, do not require knowledge of the target architectures, since they are done on the model and are immediately reflected in all implementations upon code generation, assuring consistency across platforms.

关键词： RTOS portability code generation formal modeling Event-B IoT

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Practical Memory Checking with Dr. Memory

Practical Memory Checking with Dr. Memory

引用

9th annual ieee/acm international symposium on code generation and optimization (CGO)

作者： Bruening, Derek Zhao, Qin Google

ISBN: (纸本)9781612843551

Memory corruption, reading uninitialized memory, using freed memory, and other memory-related errors are among the most difficult programming bugs to identify and fix due to the delay and non-determinism linking the error to an observable symptom. Dedicated memory checking tools are invaluable for finding these errors. However, such tools are difficult to build, and because they must monitor all memory accesses by the application, they incur significant overhead. Accuracy is another challenge: memory errors are not always straightforward to identify, and numerous false positive error reports can make a tool unusable. A third obstacle to creating such a tool is that it depends on low-level operating system and architectural details, making it difficult to port to other platforms and difficult to target proprietary systems like Windows. This paper presents Dr. Memory, a memory checking tool that operates on both Windows and Linux applications. Dr. Memory handles the complex and not fully documented Windows environment, and avoids reporting false positive memory leaks that plague traditional leak locating algorithms. Dr. Memory employs efficient instrumentation techniques;a direct comparison with the state-of-the-art Valgrind Memcheck tool reveals that Dr. Memory is twice as fast as Memcheck on average and up to four times faster on individual benchmarks.

关键词： Memory Checking Shadow Memory Dynamic optimization

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A code Generator for High-Performance Tensor Contractions on GPUs 2019

A Code Generator for High-Performance Tensor Contractions on...

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17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Kim, Jinsung Sukumaran-Rajam, Aravind Thumma, Vineeth Krishnamoorthy, Sriram Panyala, Ajay Pouchet, Louis-Noel Rountev, Atanas Sadayappan, P. Ohio State Univ Columbus OH 43210 USA Pacific Northwest Natl Lab Washington DC USA Colorado State Univ Ft Collins CO 80523 USA

ISBN: (纸本)9781728114361

Tensor contractions are higher dimensional generalizations of matrix-matrix multiplication. They form the compute-intensive core of many applications in computational science and data science. In this paper, we describe a high-performance GPU code generator for arbitrary tensor contractions. It exploits domain-specific properties about data reuse in tensor contractions to devise an effective code generation schema, coupled with an effective model-driven search, to determine parameters for mapping of computation to threads and staging of data through the GPU memory hierarchy. Experimental evaluation using a set of tensor contraction benchmarks demonstrates performance improvement and/or significantly reduced code generation time over other state-of-the-art tensor contraction libraries and code generators.

关键词： code generation Tensor Contractions GPU Computing

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BOLT: A Practical Binary Optimizer for Data Centers and Beyond 2019

BOLT: A Practical Binary Optimizer for Data Centers and Beyo...

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17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Panchenko, Maksim Auler, Rafael Nell, Bill Ottoni, Guilherme Facebook Inc Menlo Pk CA 94025 USA

ISBN: (纸本)9781728114361

Performance optimization for large-scale applications has recently become more important as computation continues to move towards data centers. Data-center applications are generally very large and complex, which makes code layout an important optimization to improve their performance. This has motivated recent investigation of practical techniques to improve code layout at both compile time and link time. Although postlink optimizers had some success in the past, no recent work has explored their benefits in the context of modern data-center applications. In this paper, we present BOLT, an open-source post-link optimizer built on top of the LLVM framework. Utilizing sample-based profiling, BOLT boosts the performance of real-world applications even for highly optimized binaries built with both feedback-driven optimizations (FDO) and link-time optimizations (LTO). We demonstrate that post-link performance improvements are complementary to conventional compiler optimizations, even when the latter are done at a whole-program level and in the presence of profile information. We evaluated BOLT on both Facebook data-center workloads and open-source compilers. For data-center applications, BOLT achieves up to 7.0% performance speedups on top of profile-guided function reordering and LTO. For the GCC and Clang compilers, our evaluation shows that BOLT speeds up their binaries by up to 20.4% on top of FDO and LTO, and up to 52.1% if the binaries are built without FDO and LTO.

关键词： Fasteners optimization Layout Instruments Pipelines Bars Open source software

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Performance Upper Bound Analysis and optimization of SGEMM on Fermi and Kepler GPUs

Performance Upper Bound Analysis and Optimization of SGEMM o...

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11th ieee/acm international symposium on code generation and optimization (CGO)

作者： Lai, Junjie Seznec, Andre INRIA Paris France

ISBN: (纸本)9781467355254;9781467355247

In this paper, we present an approach to estimate GPU applications' performance upper bound based on algorithm analysis and assembly code level benchmarking. As an example, we analyze the potential peak performance of SGEMM (Single-precision General Matrix Multiply) on Fermi (GF110) and Kepler (GK104) GPUs. We try to answer the question of how much optimization space is left for SGEMM and why. According to our analysis, the nature of Fermi (Kepler) instruction set and the limited issue throughput of the schedulers are the main limitation factors for SGEMM to approach the theoretical peak performance. The estimated upper-bound peak performance of SGEMM is around 82.5% of the theoretical peak performance on GTX580 Fermi GPU and 57.6% on GTX680 Kepler GPU. Guided by this analysis and using the native assembly language, on average, our SGEMM implementations achieve about 5% better performance than CUBLAS in CUDA 4.1 SDK for large matrices on GTX580. The achieved performance is around 90% of the estimated upper-bound performance of SGEMM on GTX580. On GTX680, the best performance we achieve is around 77.3% of the estimated performance upper bound. We also describe how to use native assembly language directly in the CUDA runtime source code.

关键词： Kepler GPU Fermi GPU SGEMM CUDA Performance Upper Bound Analysis

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