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检索条件"任意字段=Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming"

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Exploring the Use of WebAssembly in HPC 23

Exploring the Use of WebAssembly in HPC

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Chadha, Mohak Krueger, Nils John, Jophin Jindal, Anshul Gerndt, Michael Benedict, Shajulin Computer Architecture and Parallel Systems Technische Universität München Germany Department of Computer Science and Engg. Indian and Institute of Information Technology Kottayam Kerala India

ISBN: (纸本)9798400700156

Containerization approaches based on namespaces offered by the Linux kernel have seen an increasing popularity in the HPC community both as a means to isolate applications and as a format to package and distribute them. However, their adoption and usage in HPC systems faces several challenges. these include difficulties in unprivileged running and building of scientific application container images directly on HPC resources, increasing heterogeneity of HPC architectures, and access to specialized networking libraries available only on HPC systems. these challenges of container-based HPC application development closely align with the several advantages that a new universal intermediate binary format called WebAssembly (Wasm) has to offer. these include a lightweight userspace isolation mechanism and portability across operating systems and processor architectures. In this paper, we explore the usage of Wasm as a distribution format for MPI-based HPC applications. To this end, we present MPIWasm, a novel Wasm embedder for MPI-based HPC applications that enables high-performance execution of Wasm code, has low-overhead for MPI calls, and supports high-performance networking interconnects present on HPC systems. We evaluate the performance and overhead of MPIWasm on a production HPC system and AWS Graviton2 nodes using standardized HPC benchmarks. Results from our experiments demonstrate that MPIWasm delivers competitive native application performance across all scenarios. Moreover, we observe that Wasm binaries are 139.5x smaller on average as compared to the statically-linked binaries for the different standardized benchmarks. © 2023 acm.

关键词： Containers

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Poster: the Problem-Based Benchmark Suite PBBS), V2 27

Poster: The Problem-Based Benchmark Suite PBBS), V2

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Anderson, Daniel Blelloch, Guy E. Dhulipala, Laxman Dobson, Magdalen Sun, Yihan Carnegie Mellon Univ Pittsburgh Pittsburgh PA USA Univ Maryland Coll Park MD USA UC Riverside Riverside Riverside CA USA

ISBN: (纸本)9781450392044

the Problem-Based Benchmark Suite (PBBS) is a set of benchmark problems designed for comparing algorithms, implementations and platforms. For each problem, the suite defines the problem in terms of the input-output relationship, and supplies a set of input instances along with input generators, a default implementation, code for checking correctness or accuracy, and a timing harness. the suite makes it possible to compare different algorithms, platforms (e.g. CPU vs CPU), and implementations using different programming languages or libraries. the purpose is to better understand how well a wide variety of problems parallelize, and what techniques/algorithms are most effective. the suite was first announced in 2012 with 14 benchmark problems. Here we describe some significant updates. In particular, we have added nine new benchmarks from a mix of problems in text processing, computational geometry and machine learning. We have further optimized the default implementations;several are the fastest available for multicore CPUs, often achieving near perfect speedup on the 72 core machine we test them on. the suite now also supplies significantly larger default test instances, as well as a broader variety, with many derived from real-world data.

关键词： benchmarking parallel algorithms performance

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parallel Block-Delayed Sequences 22

Parallel Block-Delayed Sequences

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Westrick, Sam Rainey, Mike Anderson, Daniel Blelloch, Guy E. Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450392044

programming languages using functions on collections of values, such as map, reduce, scan and filter, have been used for over fifty years. Such collections have proven to be particularly useful in the context of parallelism because such functions are naturally parallel. However, if implemented naively they lead to the generation of temporary intermediate collections that can significantly increase memory usage and runtime. To avoid this pitfall, many approaches use "fusion" to combine operations and avoid temporary results. However, most of these approaches involve significant changes to a compiler and are limited to a small set of functions, such as maps and reduces. In this paper we present a library-based approach that fuses widely used operations such as scans, filters, and flattens. In conjunction with existing techniques, this covers most of the common operations on collections. Our approach is based on a novel technique which parallelizes over blocks, with streams within each block. We demonstrate the approach by implementing libraries targeting multicore parallelism in two languages: parallel ML and C++, which have very different semantics and compilers. To help users understand when to use the approach, we define a cost semantics that indicates when fusion occurs and how it reduces memory allocations. We present experimental results for a dozen benchmarks that demonstrate significant reductions in both time and space. In most cases the approach generates code that is near optimal for the machines it is running on.

关键词： parallel programming fusion collections functional programming

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Lifetime-Based Optimization for Simulating Quantum Circuits on a New Sunway Supercomputer 23

Lifetime-Based Optimization for Simulating Quantum Circuits ...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Chen, Yaojian Liu, Yong Shi, Xinmin Song, Jiawei Liu, Xin Gan, Lin Guo, Chu Fu, Haohuan Gao, Jie Chen, Dexun Yang, Guangwen Tsinghua University Beijing China National Supercomputing Center in Wuxi Zhejiang Lab Hangzhou China Information Engineering University Zhengzhou China National Supercomputing Center in Wuxi China Tsinghua University National Supercomputing Center in Wuxi China National Research Centre of Parallel Engineering and Technology Beijing China Tsinghua University National Supercomputing Center in Wuxi Zhejiang Lab Hangzhou China

ISBN: (纸本)9798400700156

High-performance classical simulator for quantum circuits, in particular the tensor network contraction algorithm, has become an important tool for the validation of noisy quantum computing. In order to address the memory limitations, the slicing technique is used to reduce the tensor dimensions, but it could also lead to additional computation overhead that greatly slows down the overall performance. this paper proposes novel lifetime-based methods to reduce the slicing overhead and improve the computing efficiency, including, an interpretation method to deal with slicing overhead, an inplace slicing strategy to find the smallest slicing set and an adaptive tensor network contraction path refiner customized for Sunway architecture. Experiments show that in most cases the slicing overhead with our inplace slicing strategy would be less than the Cotengra, which is the most used graph path optimization software at present. Finally, the resulting simulation time is reduced to 96.1s for the Sycamore quantum processor RQC, with a sustainable single-precision performance of 308.6Pflops using over 41M cores to generate 1M correlated samples, which is more than 5 times performance improvement compared to 60.4 Pflops in 2021 Gordon Bell Prize work. © 2023 Owner/Author.

关键词： Timing circuits

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A Scalable Hybrid Total FETI Method for Massively parallel FEM Simulations 23

A Scalable Hybrid Total FETI Method for Massively Parallel F...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Lin, Kehao Zhou, Chunbao Zeng, Yan Nie, Ningming Wang, Jue Li, Shigang Feng, Yangde Wang, Yangang Yao, Kehan Yao, Tiechui Zhang, Jilin Wan, Jian Hangzhou Dianzi University Hangzhou China Computer Network Information Center Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China School of Computer Science Beijing University of Posts and Telecommunications Beijing China

ISBN: (纸本)9798400700156

the Hybrid Total Finite Element Tearing and Interconnecting (HTFETI) method plays an important role in solving large-scale and complex engineering problems. this method needs to handle numerous matrix-vector multiplications. Directly calling the vendor-optimized library for general matrix-vector multiplication (gemv) on GPU leads to low performance, since it does not consider optimizations for different matrix sizes in HTFETI, i.e. different row and column sizes. In addition, state-of-the-art graph partitioning methods cannot guarantee load balancing for HTFETI, since the matrix size is determined by the length of the subdomain boundary. To solve the problems above, we first port gemv to the multi-stream pipeline scheme and develop a new batched kernel function on GPU, which brings 15%∼30% throughput improvement and 37% average GFLOPs improvement, respectively. We also propose a multi-grained load-balancing scheme based on graph repartitioning and work-stealing, and the load imbalance ratio is down to 1.05∼1.09 from 1.5. We have successfully applied the scalable HTFETI method to simulate the whole core assembly of China Experimental Fast Reactor (CEFR) for steady-state analysis, and the efficiencies of weak scalability and strong scalability reach 78% and 72% on 12,288 GPUs, respectively. As far as we know, this is the first time that HTFETI has been used in large-scale and high-fidelity whole core assembly simulation. © 2023 Owner/Author.

关键词： Scalability

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PERFLOW: A Domain Specific Framework for Automatic Performance Analysis of parallel Applications 22

PERFLOW: A Domain Specific Framework for Automatic Performan...

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Jin, Yuyang Wang, Haojie Zhong, Runxin Zhang, Chen Zhai, Jidong Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781450392044

Performance analysis is widely used to identify performance issues of parallel applications. However, complex communications and data dependence, as well as the interactions between different kinds of performance issues make high-efficiency performance analysis even harder. Although a large number of performance tools have been designed, accurately pinpointing root causes for such complex performance issues still needs specific in-depth analysis. To implement each such analysis, significant human efforts and domain knowledge are normally required. To reduce the burden of implementing accurate performance analysis, we propose a domain specific programming framework, named PERFLOW. PERFLOW abstracts the step-by-step process of performance analysis as a dataflow graph. this dataflow graph consists of main performance analysis sub-tasks, called passes, which can either be provided by PERFLOW'S built-in analysis library, or be implemented by developers to meet their requirements. Moreover, to achieve effective analysis, we propose a Program Abstraction Graph to represent the performance of a program execution and then leverage various graph algorithms to automate the analysis. We demonstrate the efficacy of PERFLOW by three case studies of real-world applications with up to 700K lines of code. Results show that PERFLOW significantly eases the implementation of customized analysis tasks. In addition, PERFLOW is able to perform analysis and locate performance bugs automatically and effectively.

关键词： Performance Analysis Domain Specific Framework Dataflow Graph

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Scaling Graph Traversal to 281 Trillion Edges with 40 Million Cores 22

Scaling Graph Traversal to 281 Trillion Edges with 40 Millio...

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Cao, Huanqi Wang, Yuanwei Wang, Haojie Lin, Heng Ma, Zixuan Yin, Wanwang Chen, Wenguang Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China Tsinghua Univ BNRist Beijing Peoples R China Peking Univ Sch Comp Sci Beijing Peoples R China Natl Supercomp Ctr Wuxi Wuxi Jiangsu Peoples R China

ISBN: (纸本)9781450392044

Graph processing, especially high-performance graph traversal, plays a more and more important role in data analytics. the successor of Sunway TaihuLight, NEW SUNWAY, is equipped with nearly 10 PB memory and over 40 million cores, which brings the opportunity to process hundreds of trillions of edges graphs. However, the graph with an unprecedented scale also brings severe performance challenges, including load imbalance, poor locality, and irregular access of graph traversal workload. To address the scalability problem, we propose a novel 3-level degree-aware 1.5D graph partitioning, which benefits from both delegated 1D and 2D partitioning. By delegating extremely heavy vertices globally and other heavy vertices on columns and rows in the processes mesh, we break the scalability wall of previous partitioning methods. Together with sub-iteration direction optimization, core group -aware core subgraph segmenting, and a new on-chip sorting mechanism using RMA, we achieve 180,792 GTEPS on a graph with 281 trillion edges, using 103,912 processors with over 40 million cores, achieving 1.75x performance and 8x capacity compared to the previous state of the art and conforming to the Graph 500 BFS benchmark[14].

关键词： massively parallel algorithm breadth-first search heterogeneous architecture

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Boosting Performance and QoS for Concurrent GPU B+trees by Combining-Based Synchronization 23

Boosting Performance and QoS for Concurrent GPU B+trees by C...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Zhang, Weihua Zhao, Chuanlei Peng, Lu Lin, Yuzhe Zhang, Fengzhe Lu, Yunping School of Computer Science Fudan University China Institute of Big Data Fudan University China State Key Laboratory of Mathematical Engineering and Advanced Computing China Parallel Processing Institute Fudan University China Department of Computer Science Tulane University United States

ISBN: (纸本)9798400700156

Concurrent B+trees have been widely used in many systems. With the scale of data requests increasing exponentially, the systems are facing tremendous performance pressure. GPU has shown its potential to accelerate concurrent B+trees performance. When many concurrent requests are processed, the conflicts should be detected and resolved. Prior methods guarantee the correctness of concurrent GPU B+trees through lock-based or software transactional memory (STM)-based approaches. However, these methods complicate the request processing logic, increase the number of memory accesses and bring execution path divergence. they lead to performance degradation and variance in response time increasing. Moreover, previous methods do not guarantee linearizability among concurrent requests. In this paper, we design a combined-based concurrency control framework, called Eirene, for GPU B+tree to reduce the overhead of conflict detection and resolution. First, a combining-based synchronization method is designed to combine and issue requests. It combines the requests with the same key, constructs their dependence, decides the issued request, and determines their return values. Since only one request for each key is issued, key conflicts are eliminated. then, an optimistic STM method is used to reduce structure conflicts. the query and the update requests are partitioned into different kernels. For the update kernels, STM is involved only when the number of the retry reaches a threshold. Finally, a locality-aware warp reorganization optimization is proposed to improve memory behavior and reduce conflicts by exploiting the locality among requests. Evaluations on an NVIDIA A100 GPU show that Eirene is efficient (a throughput of 2.4 billion per second) and can guarantee linearizability. Compared to the state-of-the-art GPU B+tree, it can achieve a speedup of 7.43X and reduce the response time variance from 36% to 5%. © 2023 acm.

关键词： Graphics processing unit

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parallel k-Core Decomposition with Batched Updates and Asynchronous Reads 24

Parallel k-Core Decomposition with Batched Updates and Async...

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29th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2024

作者： Liu, Quanquan C. Shun, Julian Zablotchi, Igor Yale University United States MIT CSAIL United States Mysten Labs Switzerland

ISBN: (纸本)9798400704352

Maintaining a dynamic k-core decomposition is an important problem that identifies dense subgraphs in dynamically changing graphs. Recent work by Liu et al. [SPAA 2022] presents a parallel batch-dynamic algorithm for maintaining an approximate k-core decomposition. In their solution, both reads and updates need to be batched, and therefore each type of operation can incur high latency waiting for the other type to finish. To tackle most real-world workloads, which are dominated by reads, this paper presents a novel hybrid concurrent-parallel dynamic k-core data structure where asynchronous reads can proceed concurrently with batches of updates, leading to significantly lower read latencies. Our approach is based on tracking causal dependencies between updates, so that causally related groups of updates appear atomic to concurrent readers. Our data structure guarantees linearizability and liveness for both reads and updates, and maintains the same approximation guarantees as prior work. Our experimental evaluation on a 30-core machine shows that our approach reduces read latency by orders of magnitude compared to the batch-dynamic algorithm, up to a (4.05 · 105 ) -factor. Compared to an unsynchronized (non-linearizable) baseline, our read latency overhead is only up to a 3.21-factor greater, while improving accuracy of coreness estimates by up to a factor of 52.7. © 2024 Copyright held by the owner/author(s).

关键词： Data structures

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TileSpGEMM: A Tiled Algorithm for parallel Sparse General Matrix-Matrix Multiplication on GPUs 22

TileSpGEMM: A Tiled Algorithm for Parallel Sparse General Ma...

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Niu, Yuyao Lu, Zhengyang Ji, Haonan Song, Shuhui Jin, Zhou Liu, Weifeng China Univ Petr Super Sci Software Lab Beijing Peoples R China

ISBN: (纸本)9781450392044

Sparse general matrix-matrix multiplication (SpGEMM) is one of the most fundamental building blocks in sparse linear solvers, graph processing frameworks and machine learning applications. the existing parallel approaches for shared memory SpGEMM mostly use the row-row style with possibly good parallelism. However, because of the irregularity in sparsity structures, the existing row-row methods often suffer from three problems: (1) load imbalance, (2) high global space complexity and unsatisfactory data locality, and (3) sparse accumulator selection. We in this paper propose a tiled parallel SpGEMM algorithm named TileSpGEMM. Our algorithm sparsifies the tiled method in dense general matrix-matrix multiplication (GEMM), and saves each non-empty tile in a sparse form. Its first advantage is that the basic working unit is now a fixed-size sparse tile containing a small number of nonzeros, but not a row possibly very long. thus the load imbalance issue can be naturally alleviated. Secondly, the temporary space needed for each tile is small and can always be in on-chip scratchpad memory. thus there is no need to allocate an off-chip space for a large amount of intermediate products, and the data locality can be much better. thirdly, because the computations are restricted within a single tile, it is relatively easier to select a fast sparse accumulator for a sparse tile. Our experimental results on two newest NVIDIA GPUs show that our TileSpGEMM outperforms four state-of-the-art SpGEMM methods cuSPARSE, bhSPARSE, NSPARSE and spECK in 139, 138, 127 and 94 out of all 142 square matrices executing no less than one billion flops for an SpGEMM operation, and delivers up to 2.78x, 145.35x, 97.86x and 3.70x speedups, respectively.

关键词： Sparse matrix SpGEMM tiled algorithm GPU

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