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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 187-194页

作者： Liu, Huiqun Wong, D.F. Univ of Texas at Austin Austin TX United States

Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. this paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

关键词： field programmable gate arrays

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LevelST: Stream-based Accelerator for Sparse Triangular Solver 24

LevelST: Stream-based Accelerator for Sparse Triangular Solv...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： He, Zifan Song, Linghao Lucas, Robert F. Cong, Jason University of California Los Angeles Los Angeles United States Ansys Inc. Livermore United States

ISBN: (纸本)9798400704185

Over the past decade, much progress has been made to advance the acceleration of sparse linear operators such as SpMM and SpMV on FPGAs. Nevertheless, few works have attempted to address sparse triangular solver (SpTRSV) acceleration, and the performance boost is limited. SpTRSV is an elementary linear operator for many numerical methods, such as the least-square method. these methods, among others, are widely used in various areas, such as physical simulation and signal processing. therefore, accelerating SpTRSV is crucial. However, many challenges impede accelerating SpTRSV, including (1) resolving dependencies between elements during forward or backward substitutions, (2) random access and unbalanced workloads across memory channels due to sparsity, (3) latency incurred by off-chip memory access for large matrices or vectors, and (4) data reuse for an unpredictable data sharing pattern. To address these issues, we have designed LevelST, the first FPGA accelerator leveraging high bandwidth memory (HBM) for solving sparse triangular systems. LevelST features (1) algorithm-hardware co-design of stream-based dependency resolution with reduced off-chip data movement, (2) resource sharing that improves resource utilization to scale up the architecture, (3) index modulo scheduling to balance workload, and (4) selective data prefetching from off-chip memory. LevelST is prototyped on an AMD Xilinx U280 HBM FPGA and evaluated with 16 sparse triangular matrices. Compared with the NVIDIA V100 and RTX 3060 GPUs over the cuSPARSE library, LevelST achieves a 2.65x speedup and 9.82x higher energy efficiency than the best of the V100 GPU and RTX 3060 GPU. the code is released on https://***/OswaldHe/LevelST (DOI: https://***/10.5281/zenodo.10463345). © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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FPGA-based hardware implementation of generalized profile search using online arithmetic

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 101-110页

作者： Mosanya, Emeka Sanchez, Eduardo Swiss Federal Inst of Technology Lausanne Switzerland

this paper describes the hardware implementation of the Generalized Profile Search algorithm using online arithmetic and redundant data representation. this is part of the GenStorm project, aimed at providing a dedicated computer for biological sequence processing based on reconfigurable hardware using FPGAs. the serial evaluation of the result made possible by a redundant data representation leads to a significant increase of data throughput in comparison with standard non redundant data coding.

关键词： field programmable gate arrays

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Trading quality for compile time: Ultra-fast placement for FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 157-166页

作者： Sankar, Yaska Rose, Jonathan Univ of Toronto Toronto Canada

the placement phase of the compile process and an ultrafast placement algorithm targeted to field programmable gate arrays (FPGA) are presented. the algorithm is based on a combination of multiple-level, bottom-up clustering and hierarchical simulated annealing. It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restricted to a short run time. In addition, operating on its fastest mode, this tool can provide an accurate estimate of the wirelength achievable with good quality placement. this can be used in conjunction with a routing predictor, to determine the routability of a given circuit on a given FPGA device.

关键词： field programmable gate arrays

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the Use of FPGA Evaluation Board as Data Acquisition and Pre-processing System for Synthetic Aperture Radar 16

The Use of FPGA Evaluation Board as Data Acquisition and Pre...

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16th international Radar symposium (IRS)

作者： Drozdowicz, Jedrzej Samczynski, Piotr Wielgo, Maciej Gromek, Damian Klincewicz, Karol Warsaw Univ Technol Inst Elect Syst Warsaw Poland

ISBN: (纸本)9783954048533

Experiments on Synthetic Aperture Radar require a data acquisition and storage system. Custom-made systems are well suited to this specific application, but the development of such a system is both time and resource consuming. the use of an off-the-shelf FPGA evaluation board with interchangeable analogue to digital converter cards as a data acquisition and pre-processing system was proposed. Such an approach allows not only for operation with different analogue front-ends, but also for the implementation of data pre-processing, such as modulation and decimation. the modulation makes further processing easier and the filtration-decimation reduces the size of the data stream. A complete system was tested thoroughly during a ground-based experiment and is now ready for airborne testing. As there are unused resources in the FPGA, they will be utilized in the future for the implementation of real-time processing.

关键词： Data Collection Methods Synthetic aperture radar field programmable gate arrays analog digital converter real-time process dimensional data Board Pretreatment

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Satisfiability-based layout revisited: Detailed routing of complex FPGAs via search-based Boolean SAT

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 167-175页

作者： Nam, Gi-Joon Sakallah, Karem A. Rutenbar, Rob A. Univ of Michigan Ann Arbor United States

A new search-based satisfiability (SAT) formulation that can handle entire field programmable gate array (FPGA), routing all nets concurrently is presented. the approach relies on a recently developed SAT engine that uses systematic search with conflict directed nonchronological backtracking, capable of handling very large SAT instances. Preliminary experimental results suggest that this approach to FPGA routing is more viable than earlier binary decision diagram-based method.

关键词： field programmable gate arrays

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String matching on multicontext FPGAs using self-reconfiguration

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 217-226页

作者： Sidhu, Reetinder P.S. Mei, Alessandro Prasanna, Viktor K. Univ of Southern California Los Angeles CA United States

An approach for runtime mapping is proposed that utilizes self-reconfigurability of multicontext field programmable gate arrays (FPGA) to achieve very high speedups over existing approaches. the idea is to design and map logic onto a multicontext FPGA that in turn maps problem instance dependent logic onto other contexts of the same FPGA. As a result, computer aided design tools need to be used just once for each problem and not once for every problem instance as is usually done.

关键词： field programmable gate arrays

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Probabilistic delay budgeting for soft realtime applications 06

Probabilistic delay budgeting for soft realtime applications

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7th international symposium on Quality Electronic Design

作者： Ghiasi, Soheil Huan, Po-Kuan Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)0769525237

Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their "expected delay" over input data space. this paradigm shaft calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multimedia applications on FPGAs show about 20% and 19% average energy and area improvement, respectively.

关键词： Timing Delay effects Hardware Flow graphs Application software Algorithm design and analysis Data flow computing Design methodology Stochastic processes field programmable gate arrays

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Configuration cloning: Exploiting regularity in dynamic DSP architectures

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 81-89页

作者： Park, S.R. Burleson, W. Univ of Massachusetts Amherst United States

A FPGA configuration method named configuration cloning is developed to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the configuration bit-stream already resident in a FPGA. the method resulted in speed and power improvement over off-chip partial reconfiguration techniques, while not requiring additional interconnects and control hardware. Cloning requires only a small amount of hardware overhead. Digital signal processing applications are discussed to demonstrate the order of magnitude reductions in configuration time and power.

关键词： field programmable gate arrays

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Full-system chip multiprocessor power evaluations using FPGA-based emulation

Full-system chip multiprocessor power evaluations using FPGA...

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ISLPED'08: 13th acm/IEEE international symposium on Low Power Electronics and Design

作者： Bhattacharjee, Abhishek Contreras, Gilberto Martonosi, Margaret Department of Electrical Engineering Princeton University

ISBN: (纸本)9781605581095

the design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS, Activity counters programmed into the cores feed per-component microarchitectural power models. these models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35 X speedup compared to full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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