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检索条件"任意字段=Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays"

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A 17ps time-to-digital converter implemented in 65nm technology

A 17ps time-to-digital converter implemented in 65nm technol...

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Favi, Claudio Charbon, Edoardo École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781605584102

this paper presents a new architecture for time-to-digital enabling a time resolution of 17ps over a range 50ns with a conversion rate of 20MS/s. the proposed , implemented in a 65nm FPGA system, consists a pipelined interpolating time-to-digital converter (TDC). the TDC comprises a coarse time discriminator and ne delay line, capable of sustained operation at a clock of 300MHz. A Turbo version of the circuit implements pipelined interpolating TDC with suppressed dead to reach a conversion rate of 300MS/s at the expense a systematic asymmetry that requires fast error correction. TDCs proposed in this paper can be compensated process, voltage, and temperature (PVT) variations using conventional charge pump based feedback or a digital technique. Results demonstrate the suitability the approach for a variety of applications involving precision ultra-fast time discrimination, such as optical sensing, time-of-ight cameras, high throughput comlinks, RADARs, etc. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Flexible multi-mode embedded floating-point unit for field programmable gate arrays

Flexible multi-mode embedded floating-point unit for field p...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Chong, Yee Jern Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605584102

Performance of field programmable gate arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floatingpoint units on FPGAs consume a large amount of resources. this makes FPGAs less attractive for use in floating-point intensive applications. therefore, there is a need for embedded floating-point units (FPUs) in FPGAs. However, if unutilized, embedded FPUs waste space on the FPGA die. To overcome this issue, we propose a flexible multi-mode embedded FPU for FPGAs that can be configured to perform a wide range of operations. the floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on our FPGA with embedded FPU blocks. the results using our embedded FPUs showed a mean area improvement of 5.2 times and a mean delay improvement of 5.8 times for the doubleprecision benchmarks, and a mean area improvement of 4.4 times and a mean delay improvement of 4.2 times for the single-precision benchmarks. Copyright 2009 acm.

关键词： Adders

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Fast and scalable packet classification using perfect hash

Fast and scalable packet classification using perfect hash

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Puš, Viktor Korenek, Jan CESNET z. s. p. o. Zikova 4 160 00 Prague Czech Republic Faculty of Information Technology Brno University of Technology Bozetechova 2 612 66 Brno Czech Republic

ISBN: (纸本)9781605584102

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them cancompete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. the solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. the algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. this makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Optimizations for a highly cost-efficient programmable logic architecture 98

Optimizations for a highly cost-efficient programmable logic...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Veenstra, Kerry Pedersen, Bruce Schleicher, Jay Sung, Chiakang Altera Corp San Jose CA United States

ISBN: (纸本)9780897919784

Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. this paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.

关键词： programmable logic controllers

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Towards reliable 5Gbps wave-pipelined and gbps surfing interconnect in 65nm FPGAs

Towards reliable 5Gbps wave-pipelined and gbps surfing inter...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Teehan, Paul Lemieux, G.F. Greenstreet, R. Dept. of ECE University of British Columbia Canada Dept. of Computer Science University of British Columbia Canada

ISBN: (纸本)9781605584102

FPGA user clocks are slow enough that only a fraction of the interconnect's is actually used. there may be an opportunity use throughput-oriented interconnect to decrease routing and wire area using on-chip serial signaling, especially datapath designs which operate on words instead of bits. To so, these links must operate reliably at very high bit rates. We wave pipelining and surfing source-synchronous schemes the presence of power supply and crosstalk noise. In particular, noise is a critical modeling challenge;better models are for FPGA power grids. Our results show that wave pipelining operate at rates as high as 5Gbps for short links, but it is sensitive to noise in longer links and must run much slower to reliable. In contrast, surfing achieves a stable operating bit rate of 3Gbps and is relatively insensitive to noise. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Managing pipeline-reconfigurable FPGAs 98

Managing pipeline-reconfigurable FPGAs

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cadambi, Srihari Weener, Jeffrey Goldstein, Seth Copen Schmit, Herman thomas, Donald E. Carnegie Mellon Univ Pittsburgh PA United States

ISBN: (纸本)9780897919784

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. the result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

关键词： field programmable gate arrays

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High-performance carry chains for FPGAs 98

High-performance carry chains for FPGAs

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Hauck, Scott Hosler, Matthew M. Fry, thomas W. Northwestern Univ Evanston IL United States

ISBN: (纸本)9780897919784

Carry chains are an important consideration for most computations, including FPGAs. Current FPGAs dedicate a portion of their logic to support these demands via a simple ripple carry scheme. In this paper we demonstrate how more advanced carry constructs can be embedded into FPGAs, providing significantly higher performance carry computations. We redesign the standard ripple carry chain to reduce the number of logic levels in each cell. We also develop entirely new carry structures based on high performance adders such as Carry Select, Carry Lookahead, and Brent-Kung. Overall, these optimizations achieve a speedup in carry performance of 3.8 times over current architectures.

关键词： field programmable gate arrays

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Partitioning sequential circuits on dynamically reconfigurable FPGAs

Partitioning sequential circuits on dynamically reconfigurab...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Chang, Douglas Marek-Sadowska, Malgorzata Univ of California Santa Barbara Santa Barbara United States

A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect is time-multiplexed. thus for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit, and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enhanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISC AS'89 sequential benchmark circuits. the experimental results show that the enhanced FDS reduces communication costs by 27.5% with only a 1.1% increase in the gate cost compared to traditional FDS.

关键词： field programmable gate arrays

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FPCNA: A field programmable carbon nanotube array

FPCNA: A field programmable carbon nanotube array

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Dong, Chen Chilstedt, Scott Chen, Deming Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign Urbana-Champaign United States

ISBN: (纸本)9781605584102

Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architecture known as FPCNA. We define novel CNT and nanoswitch based components and characterize these components considering nanospecific process variations, including the variation caused by the random mixture of metallic and semiconducting CNTs. To evaluate the architecture, we develop a variation-aware physicaldesign flow which can handle both Gaussian and non-Gaussian random variables using variation-aware placement and routing. When FPCNA is evaluated with this CAD flow, we see a 2.67 performance gain over a baseline CMOS FPGA at the same technology node (at a 95% performance yield). In addition, FPCNA offers a 4.5 footprint reduction compared to the baseline FPGA. these results demonstrate the potential of using CNTs and nanoswitches to build high performance FPGA circuits. Copyright 2009 acm.

关键词： Carbon nanotubes

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Bridging fault detection in FPGA interconnects using IDDQ 98

Bridging fault detection in FPGA interconnects using IDDQ

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Zhao, L. Walker, D.M.H. Lombardi, F. Texas A&M Univ College Station TX United States

ISBN: (纸本)9780897919784

this paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) field programmable gate arrays (FPGAs). the proposed approach detects bridging faults and is based on quiescent current (IDDQ) monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.

关键词： field programmable gate arrays

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