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检索条件"任意字段=Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays"

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GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths 16

GPU-Accelerated High-Level Synthesis for Bitwidth Optimizati...

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Kapre, Nachiket Ye, Deheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781450338561

Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc's GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10-1000x speedups for range analysis and 50-200x speedups for bitwidth allocation when comparing NVIDIA K20 GPU implementation to an Intel Core i5-4570 CPU while maintaining identical solution quality across various benchmarks. this allows us to generate tailor-made RTL with minimum bitwidths in hundreds of milliseconds instead of hundreds of minutes when starting from high-level C descriptions of dataflow computations.

关键词： field programmable gate arrays (FPGA)

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Choose-your-own-adventure routing: Lightweight load-time defect avoidance

Choose-your-own-adventure routing: Lightweight load-time def...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Rubin, Raphael DeHon, André Computer and Information Science University of Pennsylvania 3330 Walnut Street Philadelphia PA 19104 United States Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd Street Philadelphia PA 19104 United States

ISBN: (纸本)9781605584102

Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. the fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable hannel width, routes can tolerate 0.01% switch defect rates, raising yield from essentially 0% to near 100%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Circuit partitioning with complex resource constraints in FPGAs 98

Circuit partitioning with complex resource constraints in FP...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Liu, Huiqun Zhu, Kai Wong, D.F. Univ of Texas at Austin Austin TX United States

ISBN: (纸本)9780897919784

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing capacity and diverse resource types in the new FPGA architectures. We propose a network flow based method to optimally check whether a circuit or a sub-circuit is feasible for a set of available heterogeneous resources. the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g. logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g. Actel's ES6500 FPGA family).

关键词： field programmable gate arrays

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A hardware framework for the fast generation of multiple ong-period random number streams

A hardware framework for the fast generation of multiple ong...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Dalal, Ishaan L. Stefan, Deian Dept. of Electrical Engineering Cooper Union New York NY 10003 United States

ISBN: (纸本)9781595939340

Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality pseudo-random number generators (PRNG), such as the Mersenne Twister, are often based on binary linear recurrences and have extremely long periods (more than 21024). Many software implementations of such PRNGs exist, but hardware implementations are rare. We have developed an optimized, resource-efficient parallel framework for this class of random number generators that exploits the underlying algorithm as well as FPGA-specific architectural features. the framework also incorporates fast "jump-ahead" capability for these PRNGs, allowing simultaneous, independent sub-streams to be generated in parallel by partitioning one long-period pseudorandom sequence. We demonstrate parallelized implementations of three types of PRNGs - the 32-, 64- and 128-bit SIMD Mersenne Twister - on Xilinx Virtex-II Pro FPGAs. their area/throughput performance is impressive: for example, compared clock-for-clock with a previous FPGA implementation, a "two-parallelized" 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350 MHz for a throughput of 22.4 Gbps, which is 5.5x faster than the older FPGA implementation and 7.1x faster than a dedicated software implementation. the quality of generated random numbers is verified with the standard statistical test batteries diehard and TestU01. We also present two real-world application studies with multiple RNG streams: the Ziggurat method for generating normal random variables and a Monte Carlo photon-transport simulation. the availability of fast long-period random number generators with multiple streams accelerates hardware-based scientific simulations and allows them to scale to greater complexities. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Technology mapping for FPGAs with embedded memory blocks 98

Technology mapping for FPGAs with embedded memory blocks

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cong, Jason Xu, Songjie Univ of California Los Angeles CA United States

ISBN: (纸本)9780897919784

Modern field programmable gate arrays (FPGAs) provide embedded memory blocks (EMBs) to be used as on-chip memories. In this paper, we explore the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. We propose a general technology mapping problem for FPGAs with EMBs for area and delay minimization and develop an efficient algorithm based on the concepts of Maximum Fanout Free Cone (MFFC) and Maximum Fanout Free Subgraph (MFFS), named EMB_Pack, which minimizes the area after or before technology mapping by using EMBs while maintaining the circuit delay. We have tested EMB_Pack on MCNC benchmarks on Altera's FLEX10K device family. the experimental results show that compared with the original mapped circuits generated from CutMap without using EMBs, EMB_Pack as postprocessing can further reduce up to 10% of the area on the mapped circuits while maintaining the layout delay by making efficient use of available EMB resources. Compared with CutMap-e without using EMBs, EMB_Pack as pre-mapping processing followed by CutMap-e can reduce 6% of the area while maintaining the circuit optimal delay.

关键词： field programmable gate arrays

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SmartOpt: An industrial strength framework logic synthesis

SmartOpt: An industrial strength framework logic synthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jang, Stephen Wu, Dennis Jarvin, Mark Chan, Billy Chung, Kevin Mishchenko, Alan Brayton, Robert Xilinx Inc United States University of California Berkeley United States

ISBN: (纸本)9781605584102

In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial FPGAs. this paper presents a framework (SmartOpt) for mapping complex FPGA architectures to a simple netlist model, which can be supported by academic tools. SmartOpt was applied to leverage the algorithms implemented in the ABC package and to study their relative contributions. this work is integrated into the Xilinx ISE 11.1 software flow for FPGAs and shows significant improvements in both the LUT count and performance of large industrial circuits described in HDL. Xilinx Synthesis Technology (XST) reference flow was compared experimentally against the same flow augmented by SmartOpt. When applied to a set of 20 large industrial Virtex-5 benchmarks ranging from 17K to 69K 6- LUTs, the augmented flow produced 8.3% fewer LUTs and led to 2.1% higher operating frequency while keeping runtimes reasonable. With dual-LUT-merging, the LUT count is reduced by 22.7%, while increasing the operating frequency only by 0.7%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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FCUDA-SoC: Platform Integration for field-programmable SoC with the CUDA-to-FPGA Compiler 16

FCUDA-SoC: Platform Integration for Field-Programmable SoC w...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Nguyen, Tan Gurumani, Swathi Rupnow, Kyle Chen, Deming Adv Digital Sci Ctr Singapore Singapore Univ Illinois Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)9781450338561

throughput oriented high level synthesis allows efficient design and optimization using parallel input languages. Parallel languages offer the benefit of parallelism extraction at multiple levels of granularity, offering effective design space exploration to select efficient single core implementations, and easy scaling of parallelism through multiple core instantiations. However, study of high level synthesis for parallel languages has concentrated on optimization of core and on-chip communications, while neglecting platform integration, which can have a significant impact on achieved performance. In this paper, we create an automated flow to perform efficient platform integration for an existing CUDAto-RTL throughput oriented HLS, and we open source the FCUDA tool, platform integration, and benchmark applications. We demonstrate platform integration of 16 benchmarks on two Zynq-based systems in bare-metal and OS mode. We study implementation optimization for platform integration, compare to an embedded GPU (Tegra TK1) and verify designs on a Zedboard Zynq 7020 (bare-metal) and Omnitek Zynq 7045 (OS).

关键词： System-on-chip

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Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation 98

Boolean matching for complex PLBs in LUT-based FPGAs with ap...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cong, Jason Hwang, Yean-Yow Univ of California Los Angeles CA United States

ISBN: (纸本)9780897919784

In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but also can implement some wide functions of more than K variables. We apply previous and develop new functional decomposition methods to match wide functions to PLBs. We can determine exactly whether a given wide function can be implemented with a XC4000 CLB or other three PLB architectures (including the XC5200 CLB). We evaluate functional capabilities of the four PLB architectures on implementing wide functions in MCNC benchmarks. Experiments show that the XC4000 CLB can be used to implement up to 98% of 6-cuts and 88% of 7-cuts in MCNC benchmarks, while two of the other three PLB architectures have a smaller cost in terms of logic capability per silicon area. Our results are useful for designing future logic unit architectures in LUT based FPGAs.

关键词： field programmable gate arrays

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Towards automated ECOs in FPGAs

Towards automated ECOs in FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Andrew Brown, Stephen Zhu, Jianwen Safarpour, Sean Electrical and ComputerEngineering University of Toronto Canada Toronto Technology Center Altera Corporation Canada

ISBN: (纸本)9781605584102

During the FPGA design flow, engineering change orders (ECOs) have become an essential methodology to apply late-stage specification changes and bug fixes. ECOs are beneficial since they are applied directly to a place-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which has an unpredictable impact on the design's final correctness and end costs. As a solution, we introduce an automated method to tackle the ECO problem. Specifically, we introduce a resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design;thereby removing the inefficient manual effort required by a designer. Our technique is robust enough to handle a wide range of changes. Furthermore, our technique can successfully make late-stage functional changes while minimally perturbing the place-and-routed netlist: something that is necessary for ECOs. When applied to several benchmarks on Altera's Stratix architecture, we show that our approach can automatically apply ECOs in over 80% of the cases presented. Furthermore, our technique does this with a minimal impact to the circuit performance where on average over 90% of the placement and routing wires remain unchanged. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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CMOS continuous-time field programmable analog array

CMOS continuous-time field programmable analog array

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proceedings of the 1997 acm 5th international symposium on field-programmable gate arrays, FPGA

作者： Looby, C.A. Lyden, C. Univ Coll Cork Ireland

A circuit design for a field programmable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to implement the user's chosen circuit. the configurable connections are realized by CMOS switches and a new innovation is that these are either buffered or nulled to cancel parasitic error. the function blocks are Op-Amps combined with passive networks which allow programmable transfer functions with accuracy insensitive to variations in process parameters and environment. the intended application area is the rapid development of analog circuits which are presently prototyped by PCBs stuffed with Op-Amp and passive components. the concept has been demonstrated on a CMOS IC and the resulting performance shows the feasibility of this approach to general purpose FPAA technology.

关键词： CMOS integrated circuits

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