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Variable input delay CMOS logic for low power design

Variable input delay CMOS logic for low power design

引用

18th International conference on VLSI design/4th International conference on Embedded systems design

作者： Raja, T Agrawal, VD Bushnell, ML Transmeta Corp Santa Clara CA 95054 USA

ISBN: (纸本)0769522645

Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (C-MOS) technology. the time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. this is accomplished by inserting selectively sized "permanently on" series. transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58% over an unoptimized design. this power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on non-critical paths. the use of the variable input delay gates drastically reduced the required number of delay buffers.

关键词： CMOS integrated circuits

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Improved design and implementation of network intrusion detection system for gigabit network traffic using FPGA

Improved design and implementation of network intrusion dete...

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18th International conference on Computer Applications in Industry and Engineering 2005, CAINE 2005

作者： Patel, Parimal Tummala, Ashok Kumar Ramineni, Hari Babu Lin, Wei-Ming Department of Electrical Engineering University of Texas at San Antonio 6900 North Loop 1604 West San Antonio TX 78249 United States

ISBN: (纸本)9781604234817

As networks become faster there is an emerging need for security analysis techniques that can keep up with the increased network throughput. the software Intrusion Detection systems (IDS), often included in the operating system of a "firewall" node, evaluate the identifications of a packet directed toward the network to find intruders, but these systems are limited in performance due to the sequential nature of the imbedded processors employed in the system. One alternative is to develop a hardware-based Network IDS, which operates on rules downloaded by IT personnel in real-time such that the system reacts to it by blocking unauthorized traffic. the packet headers must be searched quickly and efficiently with the rules database loaded in the system. the amount of time the search takes will depend on the number of rules loaded into the system and how they are accessed. this paper presents improved design and implementation of a scalable architecture of a hardwarebased high speed NIDS. the architecture is scalable from a protocol point of view and the rule database can be securely updated in real-time without affecting the normal functionality. the system is designed using Xilinx's Virtex-IIPro Field Programmable Gate Arrays (FPGA) devices which perform fast and efficient hardware packet serialization, de-serialization, rule comparison, and packets forwarding or rejection depending on the comparison result and the rule's action field. the development and testing has been successful as implemented in a 1 Gbps network.

关键词： Intrusion detection

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design of multi-ghz asynchronous pipelined circuits in MOS current-mode logic

Design of multi-ghz asynchronous pipelined circuits in MOS c...

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18th International conference on VLSI design: Power Aware design of VLSI systems

作者： Kwan, Tin Wai Shams, Maitham Department of Electronics Carleton University Ottawa Ont. K1S 5B6 Canada

this paper introduces the implementation of asynchronous pipelined circuits in MOS Current-Mode Logic (MCML). C-element and double-edge-triggered flip-flop are implemented in MCML and used in so-called micropipeline circuits. the effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout simulation results, an asynchronous MCML four-stage FIFO implemented in a standard 0.18μm CMOS technology demonstrates a throughput of 4 GHz while dissipating 3.7 mW. the MCML micropipeline C-element dissipates up to four times less power compared to its conventional static CMOS counterpart at the same throughput of 1.9 GHz. © 2005 IEEE.

关键词： MOS devices

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A principal component neural network-based face recognition system and its ASIC implementation

A principal component neural network-based face recognition ...

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18th International conference on VLSI design: Power Aware design of VLSI systems

作者： Prasanna, Chakka Siva Sai Sudha, N. Kamakoti, V. Department of Computer Science and Engineering Indian Institute of Technology Madras India

ISBN: (纸本)0769522645

Principal Component Analysis (PCA) finds wide usage in computer-aided vision applications and one such application is face recognition. the neural network that performs PCA is called a Principal Component Neural Network (PCNN). this paper presents a new PCNN-based face recognition system. the proposed recognition system can tolerate local variations in the face such as expression changes and directional lighting. An optimal digital hardware design is proposed for PCNN. An ASIC implementation of the proposed design yields a throughput of processing about 11,000 inputs per second during the training phase and about 19,000 inputs per second during the retrieval phase. the customized hardware-based recognition is about 105 times faster than a software-based recognition in a PC. Such results are valuable for high-speed applications. © 2005 IEEE.

关键词： Application specific integrated circuits

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design of a low power image watermarking encoder using dual voltage and frequency

Design of a low power image watermarking encoder using dual ...

引用

18th International conference on VLSI design: Power Aware design of VLSI systems

作者： Mohanty, Saraju P. Ranganathan, N. Balakrishnan, K. Dept. of Computer Science and Engineering University of North Texas Denton TX 76203 United States Dept. of Computer Science and Engineering University of South Florida Tampa FL 33620 United States

ISBN: (纸本)0769522645

In this paper, we propose a VLSI architecture and provide prototype implementation of a chip that can insert both invisible and visible watermarks in DCT domain. To our knowledge, this is the firstever low power watermarking chip having such watermarking functionalities. Various techniques, such as multiple voltages, multiple frequency, and clock gating are incorporated to reduce power consumption of the chip. the proposed architecture has a three stage pipeline structure and also uses parallelism to improve the overall performance. A prototype chip is designed and verified using various Cadence and Synopsys tools using TSMC 0.25μ technology. It runs at a dual frequency of 280M H z and 70M H z and at a dual voltage of 2.5V and 1.5V and contains 1.4M transistors. the average power consumption of the chip is estimated to be 0.3mW, which is five times less than its single supply voltage and single frequency operation. © 2005 IEEE.

关键词： VLSI circuits

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Remote data monitoring and data analysis for substations: A case study in implementation

Remote data monitoring and data analysis for substations: A ...

引用

CIRED 2005 - 18th International conference and Exhibition on Electricity Distribution

作者： David Dolezilek Brian McDermott Schweitzer Engineering Laboratories Inc. USA

Today's intelligent electronic devices (IEDs) and robust communications processors contain large amounts of valuable substation data that have been available for years but largely overlooked. Initial integration efforts by most vendors focused solely on providing data access and control of Supervisory Control and Data Acquisition (SCADA) type data from the IEDs to replace separate SCADA hardware such as RTUs. Following the RTU replacement method led many vendors to use SCADA protocols to retrieve these data for use in supervisory operation. Choosing to use SCADA protocols, such as Modbus ® , DNP, and UCA led to the problem that data unsupported by these protocols were trapped in the IED and unavailable. Stranded data include historical performance information, equipment monitoring data, device diagnostic data, automation data, as well as settings and configuration information. A few innovative utilities have been managing these data through remote monitoring and making them available for use by all divisions of the company. Today's data tools and communications methods allow every utility to take advantage of these data to truly manage their power systems. this paper is a case study of remote data monitoring and data analysis design and techniques. this remote monitoring technology greatly reduces power system operation and maintenance (O&M) costs while providing valuable information to system planning and operating departments.

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design and implementation of a SIP-based VoIP architecture

Design and implementation of a SIP-based VoIP architecture

引用

18th International conference on Advanced Information Networking and Applications

作者： Zeadally, S Siddiqui, F Wayne State Univ High Speed Networking Lab Dept Comp Sci Detroit MI 48202 USA

ISBN: (纸本)0769520510

the emergence of the Session Initiation Protocol (SIP) promises simple and efficient handling of multimedia sessions among multiple users. In this work, we present the design and implementation of a VoIP system based on SIP. Our SIP-based VoIP system provides a wide range of services multi-point call, multiple audio encoding formats, and complex functionalities such as call muting and call-hold facilities, and personal mobility support.

关键词： Voice/data communication systems

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design and implementation of multi-user 3D-virtual space with QoS awareness based on multi-agent framework

Design and implementation of multi-user 3D-virtual space wit...

引用

18th International conference on Advanced Information Networking and Applications

作者： Ohmae, R Suganuma, T Shiratori, N Tohoku Univ Grad Sch Informat Sci Elect Commun Res Inst Sendai Miyagi 980 Japan

ISBN: (纸本)0769520510

Generally, the 3D-virtual space applications need powerful image processing capability of computer platform and broadband network environment. therefore, user must perform appropriate setting of the system to receive the service from the virtual space with comfortable QoS, under the circumstances when computer and network resource are changing in almost every moment. this research is aiming for the improvement in convenience of user of 3D-virtual space system by automatic QoS control mechanism. In this paper we propose a design and implementation of 3D-virtual space with QoS awareness based on multiagent framework.

关键词： Multi agent systems

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Architectural design of a DSP scripting language for mobile multimedia terminals

Architectural design of a DSP scripting language for mobile ...

引用

18th International conference on Advanced Information Networking and Applications

作者： Takahashi, K Mori, E Nokia Research Center Nokia Japan Co. Ltd. Finland

ISBN: (纸本)0769520510

Mobile terminals such as mobile phones are adopting a dual core processor having MPU core and DSP core inside. Dual core processor significantly benefits mobile terminals in terms of performance and power consumption. However it makes the software development more complicated because both MPU and DSP requires its own development process. In order to improve the efficiency of software development with dual core processor, we Propose a DSP scripting language and its execution environment that enables direct DSP programming from MPU side. this paper describes the design, implementation, and evaluation of the prototype system.

关键词： Multimedia systems

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A design and evaluation of Ethernet Links Bundling systems

A design and evaluation of Ethernet Links Bundling Systems

引用

18th International conference on Advanced Information Networking and Applications

作者： Guo, H Zhou, JL Ou, YK Yu, SS Huazhong Univ Sci & Technol Natl Storage Syst Lab Comp Sci & Engn Dept Wuhan 430074 Hubei Peoples R China

ISBN: (纸本)0769520510

With the number of users wanting to share and access data across enterprise networks and the Internet is increasing dramatically. network administrators now find that their server and network backbones lack the capacity to handle the increased traffic. To achieve highly efficient connectivity between backbones and servers, and higher bandwidth of server network interface, we provide a method named as Ethernet Links Bundling technology (EIB). It is a high-speed networking solution that builds upon Fast Ethernet technology to provide a dramatic increase in network performance. In this paper, the implementation methods of the EIB technology are given and performance experiments are conducted. the results show that the network bandwidth can be scaled by the bundling of multiple Ethernet links and more reliable network connectivity can be guaranteed. And we also demonstrated that the EIB technology can be practically used in real applications such as FTP and SAMBA.

关键词： local area networks network servers performance evaluation bandwidth allocation Internet telecommunication traffic Ethernet link bundling system enterprise network Internet server network interface network performance network bandwidth FTP SAMBA

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