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array placement for storage size reduction in embedded multimedia systems

Array placement for storage size reduction in embedded multi...

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proceedings of the 1997 IEEE international conference on application-specific Systems, Architectures and processors, ASAP'97

作者： De Greef, Eddy Catthoor, Francky De Man, Hugo IMEC Heverlee Belgium

In this paper we present the second stage of a two-phase strategy for reducing the required background memory sizes for a large class of data-intensive multimedia applications. This strategy is particularly useful in an embedded application context, where memory size and the corresponding power consumption are the main cost factors together with data transfers. Our strategy optimizes the storage order of arrays in memory by trying to improve the reuse of memory locations, as well for elements of the same array as for elements of different arrays. Although size reduction is the main objective, an added benefit is a reduced power consumption due to the decreased capacitive load of the memories. The memory size reduction task is part of an overall memory size and power reduction methodology called ATOMIUM, in which other tasks can increase its effectiveness (e.g. loop transformations), but it can also be used on a stand-alone base. The effectiveness of our approach is demonstrated by experimental results for some real-life multimedia applications, for which a considerable memory size reduction was obtained.

关键词： Interactive computer systems

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Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesis

Efficient exploration of nonuniform space-time transformatio...

引用

1993 international conference on application specific array processors, ASAP 1993

作者： Baltus, D.G. Allen, J. Research Laboratory of Electronics Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology CambridgeMA02139 United States

ISBN: (纸本)0818634928

A method is presented for mapping conditional affine resources equations (CAREs) into systolic-type architectures. The tasks of localization and of space-time reindexing are formulated as a single branch and broad search problem. The combined formulation allows these problems to be solved concurrently and thus ensures that true optimal solutions are derived. The employed space-time reindexing method applies different affine transforms to different array variables. The employed space-time reindexing method applies different affine transforms to different array variables. Multistage localization is effected by a search-based technique which exploits specific characteristics of the combined formulation. The search procedure comprehensively explores the space of designs defined by the constraints of these methods. For a given input, all legal designs which optimize a delay-based objective function are generated. The method has been implemented as part of the array synthesis system DESCARTES. Example problems are presented to demonstrate the feasibility of the technique. © 1993 IEEE.

关键词： Systolic arrays

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Mapping algorithms onto a multiple-chip data-driven array

Mapping algorithms onto a multiple-chip data-driven array

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1993 international conference on application specific array processors, ASAP 1993

作者： Mendelson, B. Koren, I. IBM Israel-Science and Technology Matam Haifa31905 Israel Dept. of Electrical and Computer Eng. University of Massachusetts AmherstMA01003 United States

ISBN: (纸本)0818634928

Data-driven arrays provide high levels of parallelism and pipelining for algorithms with no internal regularity. Most of the methods previously developed for mapping algorithms onto processor arrays assumed an unbounded array (i.e., one in which there will always be a sufficient number of processing elements (PEs) for the mapping). Implementing such an array is not practical. A more practical approach would be to assign the PEs to chips and map the given algorithm onto the new array of chips. The authors describe a way to directly map algorithms onto a multiple-chip data-driven array, where each chip contains a limited number of PEs. There are two optimization steps in the mapping. The first is to produce an efficient mapping by minimizing the area (i.e., the number of PEs used) as well as optimizing the performance (pipeline period and latency) for the given algorithm, or finding a trade-off between area and performance. The second is to divide the unbounded array among several chips each containing a bounded number of PEs. © 1993 IEEE.

关键词： Conformal mapping

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CMOS-based capacitive sensor array dedicated to microfluidic studies

CMOS-based capacitive sensor array dedicated to microfluidic...

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IEEE 18th international conference application-specific Systems, Architectures and processors, ASAP07

作者： Zadeh, Ebrahim Ghafar Sawan, Mohamad Jalali, Mohsen Therriault, Daniel Polystim Neurotechnologies Laboratory Dept. of Elec. Eng. École Polytechnique de Montréal Micro- and Nanofabrication Laboratory by Direct-write Dept. of Mech. Eng. École Polytechnique de Montréal

ISBN: (纸本)1424410274

We present a novel technique to study the behavior of liquids in microfluidics. For this, an array of capacitive sensor realized in CMOS circuitry is considered to detect the liquid in a channel integrated into CMOS chip. We describe a robotic-based microfluidic fabrication process and the preliminary experimental results. Also, the capacitive simulation results are displayed using a finite-element based software. © 2006 IEEE.

关键词： CMOS integrated circuits

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Embedding pyramids in array processors with pipelined busses

Embedding pyramids in array processors with pipelined busses

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proceedings of the 1990 international conference on application specific array processors

作者： Guo, Zicheng Melhem, Rami G. Dept of Electr Eng & Comput Sci Univ of Pittsburgh PA USA

ISBN: (纸本)0818690895

The concept of pipelined buses for parallel architectures diverges from the conventional exclusive access buses and offers both possibilities and challenges for significantly improving the efficiency of interprocessor communications in parallel computers. The authors present an efficient embedding of pyramids in array processors with pipelined buses. The embedding has the property that all the neighboring nodes in the pyramid are mapped to the same bus. Thus, any two neighbors in the embedded pyramid can communicate with each other using a single bus cycle.

关键词： Computer Vision

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System design of an integrated measurement electronic subsystem for bacteria detection using an electrode array and MC-1 magnetotactic bacteria

System design of an integrated measurement electronic subsys...

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IEEE 18th international conference application-specific Systems, Architectures and processors, ASAP07

作者： El Fouladi, Jaouad André, Walder Savaria, Yvon Martel, Sylvain IEEE EE Department École Polytechnique de Montréal Canada

ISBN: (纸本)1424410274

This paper presents a novel technique for bacteria detection. The proposed system uses MC-1 magnetotactic bacteria and measures impedance to detect the presence of pathogenic bacteria. An electrode array is connected to respective cells that are fully integrated for impedance detection. The simulated performance shows that the circuit that was designed is robust. It can detect impedances ranging from about 3KΩ to at least 100MΩ. The only limits that we have for detecting large impedances are the operation frequencies and leakage currents. The circuit is thus very robust and can adapt to a wide range of uncertainty. © 2006 IEEE.

关键词： Leakage currents

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1987 proceedings - FOURTH international IEEE VLSI MULTILEVEL INTERCONNECTION conference.

1987 PROCEEDINGS - FOURTH INTERNATIONAL IEEE VLSI MULTILEVEL...

引用

1987 proceedings - Fourth international IEEE VLSI Multilevel Interconnection conference.

作者： Anon

The following topics are dealt with: fault-tolerant computers;associative processors and memories;defect-tolerant components;systolic array processors;signal processing architectures;emerging architectures;multiprocessors;distributed systems;image processing architectures;logic and system simulation;circuit and interconnection simulation;hierarchical design and silicon compilers;logic synthesis and design languages;device modeling and simulation;testing;hardware accelerators;knowledge-based tools;WSI;packaging;physical design;automation and robotics;image processing and graphics;computer networks;parallel/multiprocessing systems;supercomputers;application-specific ICs;intelligent workstations;technology transfer;and reliabiity and maintainability. 251 papers were presented, of which 243 are published in full in the present proceedings, and 8 as abstracts only.

关键词： INTEGRATED CIRCUITS, VLSI

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Performance-scalable array architectures for modular multiplication

Performance-scalable array architectures for modular multipl...

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2000 IEEE international conference on application-specific Systems, Architectures, and processors

作者： Freking, William L. Parhi, Keshab K. Univ of Minnesota Minneapolis United States

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-world-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.

关键词： Cryptography

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Effects of compiler options on application performance

Effects of compiler options on application performance

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proceedings of the IEEE international conference on Computer Design: VLSI in Computers and processors

作者： Stewart, Katherine E. White, Steven W. Scientific & Engineering Software Inc

Compiler optimizations play a pivotal role in determining the run-time performance of an application. Performance improvements stem from path length reduction, efficient instruction selection, pipeline scheduling, and memory penalty minimization. This paper describes typical optimizations and highlights the mechanisms by which they improve performance. We categorize the described optimizations as basic, architecture specific, interprocedural, and source level. To accurately make trade-offs in the hardware design process, compiler/hardware interaction is essential in the early design stages.

关键词： Program compilers

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The PAPRICA SIMD array: Critical reviews and perspectives

The PAPRICA SIMD array: Critical reviews and perspectives

引用

1993 international conference on application specific array processors, ASAP 1993

作者： Gregoretti, F. Sansoe, C. Reyneri, L.M. Broggi, A. Conte, G. Dip. di Elettronica Politecnico di Torino Italy Dip. di Ingegneria dell'Informazione Universita di Pisa Italy Dip. di Ingegneria dell'Informazione Universita di Parma Italy

ISBN: (纸本)0818634928

The PAPRICA project started in 1988 as an experimental VLSI architecture devoted to the efficient computation of data with two-dimensional structure. The main goal of the project is to develop a subsystem that could operate as an attached processing unit to a standard workstation and in perspective as a specialized processing module in dedicated systems devoted to low level image analysis, cellular neural networks emulation, DRC algorithms. The architecture has been extensively used for basic low level image analysis tasks up to optical flow computation and feature tracking, showing encouraging performance even in the first prototype version. The authors discuss the actual implementation and present a critical analysis of the project, allowing to identify some crucial points of PAPRICA design (and of array processors in general) that must be carefully considered in the case of redesign. © 1993 IEEE.

关键词： Cellular neural networks

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