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Recursive algorithms for AR spectral estimation and their array realizations

Recursive algorithms for AR spectral estimation and their ar...

引用

proceedings of the 1990 international conference on application specific array processors

作者： Liu, Chi-Min Jen, Chein-Wei Inst of Electron Nat Chiao Tung Univ Taiwan

ISBN: (纸本)0818690895

Autoregressive (AR) spectral estimation is widely used in various fields. However, a trade-off between performance and computational complexity is sometimes faced. Two recursive computing algorithms individually applied to the wide-sense stationary and highly nonstationary environments are presented. These algorithms have good numerical properties, high computing parallelism, and data locality. VLSI arrays are designed to realize the algorithms. The algorithms and arrays provide the potential of attaining high processing speed and good performance in real-time applications.

关键词： Signal Processing

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On synthesizing application-specific array architectures from behavioral specifications

On synthesizing application-specific array architectures fro...

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1993 international conference on application specific array processors, ASAP 1993

作者： Jensen, P.M.R. Hermansen, K. Department of Communication Technology Institute of Electronic Systems Aalborg University Denmark

ISBN: (纸本)0818634928

The authors describe a design framework, Architect, being developed for synthesizing application-specific array architectures from behavioral specifications to Register-Transfer (RT) descriptions , which can be identified as a number of cooperating tasks;signal transformations, hardware mapping expressed as, in general, nonlinear mapping and scheduling function with hardware constraints, memory management and controller synthesis. The authors present novel extensions to existing formal (i.e., ILP) and heuristics methods for multiplexing and clustering allowing constrained hardware allocation. Also a novel approach for optimizing on-chip memory is presented. © 1993 IEEE.

关键词： Heuristic methods

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An efficient disk-array-based server design for a multicast video streaming system

An efficient disk-array-based server design for a multicast ...

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14th IEEE international conference on application-specific Systems, Architectures and processors

作者： Chan, PPH Lee, JYB Chinese Univ Hong Kong Dept Informat Engn Shatin Hong Kong Peoples R China

ISBN: (纸本)076951992X

Recently, a number of researchers have started to investigate new video-on-demand (VoD) architectures using batching, patching and periodic broadcasting. These architectures, compared to traditional unicast VoD systems, are much more scalable and can serve thousands or even millions of clients concurrently. Nevertheless, existing studies are usually focused on architectural issues. The problem of designing an efficient server to implement these new multicast VoD architectures has received little attention. While existing server designs using round-based schedulers can still be used, results show that such designs are sub-optimal as they do not exploit the characteristics of fixed-schedule periodic broadcasting channels. This study addresses this challenge by presenting an efficient server design for a recent multicast VoD architecture called Super-Scalar Video-on-Demand (SS-VoD). Results show that the efficient server design can increase the system capacity by 60% compared to traditional video server designs. This paper presents details of this new server design, derives a performance model, and analyzes it using numerical results.

关键词： Video on demand

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Scheduling of partitioned regular algorithms on processor arrays with constrained resources

Scheduling of partitioned regular algorithms on processor ar...

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international conference on application-specific Systems, Architectures and processors

作者： Teich, J Thiele, L Zhang, L ETH ZURICH INST TIKCH-8092 ZURICHSWITZERLAND

ISBN: (纸本)081867542X

A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: (1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories are modeled and taken into account in the optimization model. (2) Different types of processors can be handled. (3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, (4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.

关键词： array processors PROCESSOR execution time Tile partitions alternating chain algorithms Regular Integer

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An application-specific array architecture for feedforward with backpropagation ANNs

An application-specific array architecture for feedforward w...

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1993 international conference on application specific array processors, ASAP 1993

作者： Malluhi, Q.M. Bayoumi, M.A. Rao, T.R.N. Center for Advanced Computer Studies University of Southwestem Louisiana LafayetteLA70504 United States

ISBN: (纸本)0818634928

An application-specific array architecture for Artificial Neural Networks (ANNs) computation is proposed. This array is configured as a mesh-of-appendixed-trees (MAT). Algorithms to implement both the recall and the training phases of the multilayer feedforward with backpropagation ANN model are developed on MAT. The proposed MAT architecture requires only O(log N) time, while other reported techniques offer O(N) time, where N is the size of the largest layer. Beside the high speed performance, pipelining of more than one input pattern can be achieved which further improves the performance. © 1993 IEEE.

关键词： Neural networks

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Transformation techniques for serial array design

Transformation techniques for serial array design

引用

proceedings of the international conference on application specific array processors

作者： Luk, W.W.C. Oxford Univ Computing Lab Oxford United Kingdom

ISBN: (纸本)0818629673

This paper describes a design framework for developing application-specific serial array circuits. Starting from a description of the state-transition logic or a fully-parallel architecture, correctness-preserving transformations are employed to derive a wide range of implementations with different space-time trade-offs. The approach has been used in synthesizing designs based on Field-Programmable Gate arrays, and will be illustrated by the development of a number of circuits including sorters and convolvers.

关键词： Computer architecture

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Custom FPGA-based Soft-processors for Sparse Graph Acceleration 26

Custom FPGA-based Soft-Processors for Sparse Graph Accelerat...

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26th international conference on application-specific Systems, Architectures and processors (ASAP)

作者： Kapre, Nachiket Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781479919253

FPGA-based soft processors customized for operations on sparse graphs can deliver significant performance improvements over conventional organizations (ARMv7 CPUs) for bulk synchronous sparse graph algorithms. We develop a stripped-down soft processor ISA to implement specific repetitive operations on graph nodes and edges that are commonly observed in sparse graph computations. In the processing core, we provide hardware support for rapidly fetching and processing state of local graph nodes and edges through spatial address generators and zero-overhead loop iterators. We interconnect a 2D array of these lightweight processors with a packet-switched network-on-chip to enable fine-grained operand routing along the graph edges and provide custom send/receive instructions in the soft processor. We develop the processor RTL using Vivado High-Level Synthesis and also provide an assembler and compilation flow to configure the processor instruction and data memories. We outperform a Microblaze (100MHz on Zedboard) and an NIOS-II/f (100MHz on DE2-115) by 6x (single processor design) as well as the ARMv7 dual-core CPU on the Zynq SoCs by as much as 10x on the Xilinx ZC706 board (100 processor design) across a range of matrix datasets.

关键词： PROCESSOR Line graph address generator Assemblers Customs Graph algorithms performance boost Customization central processing units

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Determining longest common subsequences of two sequences on a linear array of processors

Determining longest common subsequences of two sequences on ...

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proceedings of the international conference on application specific array processors

作者： Mukherjee, Amar Univ of Central Florida Orlando United States

ISBN: (纸本)0818629673

This paper presents special-purpose linear array processor architecture for determining longest common subsequences (LCS) of two sequences. The algorithm uses systolic and pipelined architecture suitable for VLSI implementation. The algorithms are also suitable for implementation on parallel machines. We first develop a `greedy' algorithm to determine some of the LCS and then propose a generalization to determine all LCS of the given pair of sequences. Earlier hardware algorithms [Lipton and Lopresti, 85;Mukherjee, 89] were concerned with determining only the length of LCS or the edit distance of two sequences.

关键词： Algorithms

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Realization of a nonlinear digital filter on a DSP array processor

Realization of a nonlinear digital filter on a DSP array pro...

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proceedings of the 1997 IEEE international conference on application-specific Systems, Architectures and processors, ASAP'97

作者： Kwan, Hercule Powers, Edward J. Swartzlander Jr., Earl E. Univ of Texas at Austin Austin United States

This paper presents the performance evaluation of a fast third-order Volterra digital filtering algorithm mapped onto an AT&T DSP-3 parallel processor. Five different implementations are considered. Speed-up results indicate that the `time-skewing' method is currently the fastest. An application to nonlinear communication channel equalization using a 64-QAM signal constellation is presented.

关键词： Digital filters

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Partitioning schemes for circuit simulation on a multiprocessor array

Partitioning schemes for circuit simulation on a multiproces...

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1991 international conference on application specific array processors, ASAP 1991

作者： Telichevesky, Ricardo Agrawal, Prathima Trotter, John A. Department of EECS MIT CambridgeMA02139 United States ATandBell Laboratories Murray HillNJ07974 United States

ISBN: (纸本)0818692375

The factorization of sparse matrices is used in the inner loop of many engineering algorithms, including circuit simulation. This time consuming operation can be sped up by utilising muniprocessor architectures. Distributed memory architectures can overcome the memory bottleneck normally associated with shared memory machines but require a careful distribution of matrix data to the processors. In this paper we present partitioning schemes that distribute the rows of the matrix to processors to allow a better utilization of the processing resources. We also present bounds on the speedup achieveable with partitioned matrices. We demonstrate that a good partitioning strategy coupled with more sophisticated scheduling algorithms improves the overall processor utilization. © 1991 IEEE.

关键词： Circuit simulation

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