The proceedings contains 24 papers. Topics discussed include logic design, fieldprogrammablegatearrays, pipelined routing and scheduling, logic synthesis, architecture of special purpose structures, field programma...
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The proceedings contains 24 papers. Topics discussed include logic design, fieldprogrammablegatearrays, pipelined routing and scheduling, logic synthesis, architecture of special purpose structures, fieldprogrammablegatearrays partitioning, applications and bit-serial synthesis.
A methodology is presented for production-time testing of segmented channel fieldprogrammablegatearrays (FPGA). The principles of this methodology are based on configuring the uncommitted modules of the FPGA as a s...
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ISBN:
(纸本)9780897917438
A methodology is presented for production-time testing of segmented channel fieldprogrammablegatearrays (FPGA). The principles of this methodology are based on configuring the uncommitted modules of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILA). These arrays are tested by establishing appropriate conditions such as constant testability. A design approach is then proposed. This approach is based on adding a small circuitry between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. Features such number of test vectors and hardware requirements are also analyzed.
A novel field-programmable mixed-analog-digital array (FPMA) is proposed, which contains a field-programmable analog array, a field-programmable digital array, and a mixed-signal interface. This device is intended to ...
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A novel field-programmable mixed-analog-digital array (FPMA) is proposed, which contains a field-programmable analog array, a field-programmable digital array, and a mixed-signal interface. This device is intended to be used for the rapid implementation of mixed-signal circuits. The resource and architectural requirements for this array are determined by analyzing a set of sample circuits. The mixed-signal interface is constructed from converter blocks that contain configurable A/D and D/A converters, which gives some flexibility in the specification of the interface. A 1.2 μm CMOS prototype IC has been designed to demonstrate the feasibility of FPMA technology.
Area-IO provide a way to eliminate the IO bottleneck of fieldprogrammable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and the propensity of logic to demand it. Whet...
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ISBN:
(纸本)9780897917438
Area-IO provide a way to eliminate the IO bottleneck of fieldprogrammable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and the propensity of logic to demand it. Whether the incorporation of area IO into FPLD architectures has undesirable side effects is a question that has not yet been answered. In this paper, we examine the architectural impact of area-IO on FPLDs from a theoretical and experimental standpoint and show that the introduction of area IO generally improves the routability and delay of a set of benchmark circuits.
The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration betw...
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The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (rd-11) group and DEC-PRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1 [2]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm [3]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.
As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in ...
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As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently. The key feature of such architectural support is that it must be flexible enough to accommodate many different memory shapes (widths and depths) as well as allowing different numbers of independently-addressed memory blocks. This paper describes a family of centralized field-Configurable Memory architectures which consist of a number of memory arrays and dedicated mapping blocks to combine these arrays. We also present a method for comparing these architectures, and use this method to examine the tradeoffs involved in choosing the array size and mapping block capabilities.
Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel fieldprogrammablegate array (FPGA) based reconfigurable coproce...
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ISBN:
(纸本)9780897917438
Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel fieldprogrammablegate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms are developed using a Mathematics of arrays (MOA). They provide a means to generate addresses for data transfers that require less data movement than more traditional algorithms. In this manner, the address generation algorithms are acting as an intelligent data prefetching mechanism or special purpose cache controller. Software implementations have been used to provide speedups on the order of 100% over classical methods to the solution of heat transfer equations on a uniprocessor. We extend these methods to application designs for the Chameleon Coprocessor.
field-programmablegatearrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower NRE cost and rapid turnaround with the penalties of reduced spe...
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ISBN:
(纸本)0769515622
field-programmablegatearrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower NRE cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, Laser-induced MakeLink(TM)* technology is proposed as a programmable switch element. The Electrical resistance is as low as 0.8 Omega to 11 Omega, depending on the size of the link, which is 2-3 orders smaller than that of NMOS transistor in a SRAM based FPGA. Thus the speed improvement for Laser field-programmablegate Array (LFPGA) is significant. Other features of Laser-induced vertical links technology, such as small size and radiation hardness, car, also greatly improve the FPGA performance. The cluster-based LFPGA with 128 by 64 basic logic elements (BLE) is laid out under a 0.5 mum commercialized technology. The chip size is about 138mm(2).
Recently, as one dynamic reconfigurable device, optically reconfigurable gatearrays (ORGAs) that consist of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve greater than 1 Ter...
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Energy minimization is an important step in molecular modeling, with applications in molecular docking and in mapping binding sites. Minimization involves repeated evaluation of various bonded and non-bonded energies ...
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ISBN:
(纸本)9781605587219
Energy minimization is an important step in molecular modeling, with applications in molecular docking and in mapping binding sites. Minimization involves repeated evaluation of various bonded and non-bonded energies of a protein complex. It is a computationally expensive process, with runtimes typically being many hours on a desktop system. In the current article, we present acceleration of the energy evaluation phase of minimization using fieldprogrammablegatearrays. We project a multiple orders-of-magnitude speed-up over a single CPU core and a factor of 8 speed-up over our previous acceleration using an NVIDIA Tesla 1060 GPU. Copyright 2009 acm.
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