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Experimenting with buffer sizes in routers 07

Experimenting with buffer sizes in routers

引用

3rd acm/IEEE symposium on Architectures for Networking and Communications Systems, ANCS 2007

作者： Beheshti, Neda Naous, Jad Ganjali, Yashar McKeown, Nick Stanford University United States University of Toronto Canada

ISBN: (纸本)9781595939456

Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets. The underlying assumption is that the traffic is non-bursty, and that the system is operated below 85-90% utilization. In this paper, we present a test-bed for buffer sizing experiments using NetFPGA [2], a PCI-form factor board that contains reprogrammable FPGA elements, and four Gigabit Ethernet interfaces. We have designed and implemented a NetFPGA-based Ethernet switch with finely tunable buffer sizes, and an event capturing system to monitor buffer occupancies inside the switch. We show that reducing buffer sizes down to 20-50 packets does not necessarily degrade system performance.

关键词： field programmable gate arrays (FPGA)

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GNSS signal acquisition platform design

GNSS signal acquisition platform design

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2009 3rd IEEE international symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, MAPE 2009

作者： Wang, Jian Lu, Debiao Liang, Kun Shangguan, Wei School of Electronic and Information Engineering Beijing Jiaotong University Beijing China State Key Laboratory of Rail Traffic Control and Safety Beijing Jiaotong University Beijing China National Institute of Metrology Beijing China

ISBN: (纸本)9781424440740

This paper mainly focuses on a GNSS IF signal acquisition platform;the platform is comprised of RF module, control module, buffer module, transmission module and a data acquisition routine. RF module is designed as a single-circuit board to facilitate for replacement, GNSS signal is converted to IF digital signal by filtering, amplifying, down conversion and sampling in the RF module;programmable logic device is used in control module, so it is flexible and upgradeable. The entire data flow control is completed by programmable logic device;USB2.0 controller is used in transmission module, which provides high speed performance to meet the requirement of GNSS IF signal. It is used to transmit the IF digital signal to the USB bus;Data acquisition routine running on the computer collects GNSS IF digital signal from the USB bus and stores it in the computer's storage medium. ©2009 IE.

关键词： field programmable gate arrays (FPGA)

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The hardware realization of the bicubic interpolation enlargement algorithm based on FPGA

The hardware realization of the bicubic interpolation enlarg...

引用

3rd international symposium on Information Processing, ISIP 2010

作者： Zhang, Yunshan Li, Yuhui Zhen, Jie Li, Jionghao Xie, Ran Yunnan Administration College Yunnan Provincial Committee School of the CPC Kunming China Faulty of Information Engineering and Automation Kunming University of Science and Technology Kunming China

ISBN: (纸本)9780769542614

There is an improvement to the Bicubic interpolation enlargement algorithm based on the hardware parallel processing in this article. Search table method used in this paper has avoided massive cubic and the floating numbers multiply operation. It reduces the computation load greatly. Convolution operation in tow directions, level and vertical, of the 4x4 picture element matrix on FPGA has been realized by LPM. The Bicubic interpolation enlargement algorithm is completely based on the hardware parallel characteristic to realize. This method has the superiority in the computation speed and occupies on the resources. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources 13

Pipeline template and scheduling algorithm for mapping multi...

引用

23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Dong, Yazhuo Zhan, Wu Ye, Xiqing Naval Academy of Armament No. 3 Wanshou Street Haidian area Beijing City 100036 China

ISBN: (纸本)9781450319027

There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. FPGA provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a parameterized pipeline template to execute all the loop nests in sequence without FPGA reconfiguration. Five steps are designed to decide the parameters. Experiments show that the pipeline template can achieve a comparative execution cycles for a loop comparing with the special hardware structure. © 2013 Authors.

关键词： field programmable gate arrays (FPGA)

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DPICO: A high speed deep packet inspection engine using compact finite automata 07

DPICO: A high speed deep packet inspection engine using comp...

引用

3rd acm/IEEE symposium on Architectures for Networking and Communications Systems, ANCS 2007

作者： Hayes, Christopher L. Luo, Yan Department of Electrical and Computer Engineering University of Massachusetts Lowell Lowell MA 01854 United States

ISBN: (纸本)9781595939456

Deep Packet Inspection (DPI)has been widely adopted in detecting network threats such as intrusion, viruses and spam. It is challenging, however, to achieve high speed DPI due to the expanding rule sets and ever increasing line rates. A key issue is that the size of the finite automata falls beyond the capacity of on-chip memory thus incurring expensive off-chip accesses. In this paper we present DPICO a hardware based DPI engine that utilizes novel techniques to minimize the storage requirements for finite automata. The techniques proposed are modified content addressable memory (mCAM), interleaved memory banks, and data packing. The experiment results show the scalable performance of DPICO can achieve up to 17.7 Gbps throughput using a contemporary FPGA chip. Experiment data also show that a DPICO based accelerator can improve the pattern matching performance of a DPI server by up to 10 times. Copyright 2007 acm.

关键词： field programmable gate arrays (FPGA)

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A FPGA and zernike moments based near-field laser imaging detector multi-scale real-time target recognition algorithm

A FPGA and zernike moments based near-field laser imaging de...

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作者： Liu, Li-Feng Ma, Hui-Min Lu, Ming-Quan Departmnet of Electronics Engineering Tsinghua University Beijiang China

ISBN: (纸本)9780769543604

Laser imaging Detector is one direction of Detectors'development. The encounter attitude of the detector and aircraft can be arbitrary, and there may be clouds and smoke, thereby causing interference to imaging. This paper presents a stable algorithm based on Zernike moments which can effectively recognize flying plane and against the cloud and smoke interference. The paper attempts to calculate Zernike moments of an image by using FPGA, and treat them as some kinds of feature to identify target by using the Fisher classifier which can achieve a good classification result. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA and ASIC Implementation and Comparison of Multipliers 3

FPGA and ASIC Implementation and Comparison of Multipliers

引用

3rd international symposium on Devices, Circuits and Systems, ISDCS 2020

作者： Neyaz, Salwa Yasmeen Saxena, Itisha Alam, Naushad Rahman, Syed Atiqur Department of Electronics Engineering Aligarh India

ISBN: (纸本)9781728165646

The multipliers find extensive use in today's digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit and 8-bit multipliers i.e. Array, Wallace and Baugh Wooley. The implementation is done on both the FPGA and ASIC to compare the designs. The FPGA implementation is done on NEXYS 4 DDR which is equipped with Xilinx Artix-7 FPGA. The ASIC implementation is done using Cadence and Standard Cell Library 90 nm gpdk (generic process design kit). The results indicate that the Baugh Wooley incurs the minimum delay in the FPGA implementation while as the Wallace tree incurs minimum Power Delay Product in the ASIC implementation. The Baugh Wooley is the least area consuming architecture for both the FPGA and the ASIC implementation. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design of video processing and testing system based on DSP and FPGA

Design of video processing and testing system based on DSP a...

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3rd international symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment

作者： Xu, Hong Lv, Jun Chen, Xi'Ai Gong, Xuexia Yang, Chen'Na China Jiliang Univ. China

ISBN: (纸本)9780819468802

Based on high speed Digital Signal Processor (DSP) and field programmable gate Array (FPGA), a video capture, processing and display system is presented, which is of miniaturization and low power. In this system, a triple buffering scheme was used for the capture and display, so that the application can always get a new buffer without waiting;The Digital Signal Processor has an image process ability and it can be used to test the boundary of workpiece's image. A video graduation technology is used to aim at the position which is about to be tested, also, it can enhance the system's flexibility. The character superposition technology realized by DSP is used to display the test result on the screen in character format. This system can process image information in real time, ensure test precision, and help to enhance product quality and quality management.

关键词： field programmable gate arrays (FPGA)

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Design and implementation of LDPC codec for aircraft control and simulation

Design and implementation of LDPC codec for aircraft control...

引用

作者： Qi, Jinqing Zhang, Jingbin Ma, Xiaohong Sun, Yi Yu, Yan School of Information and Communication Engineering Dalian University of Technology Dalian China School of Electronic Science and Technology Dalian University of Technology Dalian China

ISBN: (纸本)9780769543604

The system is based on the platform of Altera DE2 SOPC and RS232 interface using a wireless channel environment. NIOS-II processor and FPGA hardware co-design methodology is adopted. The soft-core processor asks for a request to send codec allocation and other operations and FPGA is responsible for the major hardware codec. The LDPC codec system can achieve a two-way communication with flexible configuration, which is particularly suitable for satellite communications. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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DCT trigger for a detection of very inclined showers in the Pierre Auger surface detector Engineering Array in the new High-Resolution Front-End based on the Cyclone V FPGA

DCT trigger for a detection of very inclined showers in the ...

引用

3rd international Conference on Innovative Network Systems and Applications (iNetSApp) held in conjunction with Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Szadkowski, Zbigniew Univ Lodz Dept Phys & Appl Informat Fac High Energy Astrophys Pomorska 149 PL-90236 Lodz Poland

ISBN: (纸本)9788360810668

The paper presents the first results from the trigger based on the Discrete Cosine Transform (DCT) operating in the new Front-End Boards with Cyclone V FPGA deployed in 8 test surface detectors in the Pierre Auger Engineering Array. The patterns of the Analog-to-Digial Converter (ADC) traces generated by very inclined showers were obtained from the Auger database and from the CORSIKA simulation package supported next by OffLine reconstruction Auger platform which gives a predicted digitized signal profiles. Simulations for many variants of the initial angle of shower, initialization depth in the atmosphere, type of particle and its initial energy gave a boundary of the DCT coefficients used next for the on-line pattern recognition in the FPGA. Preliminary results have proven a right approach. We registered several showers triggered by the DCT for 120 MSps and 160 MSps.

关键词： cosmic ray apparatus cosmic ray showers Analog-to-Digial Converter trace patterns Auger database CORSIKA simulation package Cyclone V FPGA DCT coefficients DCT trigger Discrete Cosine Transform Front-End Boards OffLine reconstruction Auger platform Pierre Auger surface detector digitized signal profiles on-line pattern recognition shower initial angle variants very inclined shower detection arrays Attenuation Cyclones Detectors Discrete cosine transforms field programmable gate arrays Standards discrete cosine transforms field programmable gate arrays cosmic ray showers cyclones detector arrays Attenuation Attenuation DCT gene front-ends Spiral wood bits

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