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检索条件"任意字段=Proceedings of the 1995 ACM 3rd International Symposium on Field-Programmable Gate Arrays"

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Design and implement of BPSK modulator and demodulator based on modern DSP technology

Design and implement of BPSK modulator and demodulator based...

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2009 3rd IEEE international symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, MAPE 2009

作者： Song, Wenmiao Zhang, Jingying Yao, Qiongqiong Dept. of Electronic and Communication Engineering North China Electric Power University Baoding China

ISBN: (纸本)9781424440740

This paper presents a method to design BPSK modulator and demodulator. The method makes use of modern DSP technology which uses the tool of DSP Builder of American Altera Co. The direct digital synthesis (DDS) principle is briefly presented and used to design orthogonal cosine signal module. In demodulator, we use the low pass FIR filtering IP core to filter high frequency component. The BPSK modem is ultimately implemented on the FPGA device. This design uses MATLAB/Simulink, DSP Builder 7.2, ModelSim 6.1g and Quartusll7.2 to simulate and realize directly BPSK modulator and demodulator based on FPGA, using DSP Builder to substitute the VHDL programming, has the organic integration in modeling and hardware implementation on the same work bench. The method can greatly improve the developing efficiency, shorten developing period and reduce costs. The practice has proved the accuracy and validity of the method. ©2009 IEEE.

关键词： field programmable gate arrays (FPGA)

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The neural network PID controller for cement rotary kiln temperature based on FPGA

The neural network PID controller for cement rotary kiln tem...

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作者： Guo, Yaohua Ma, Junshuang Yao, Minglin Department of Information Engineering Tangshan College Tangshan Hebei Province China

ISBN: (纸本)9780769543604

In this paper, we discuss a method of using BP neural network to adjust PID parameters online for controlling the cement kiln temperature. First, according to the principle of the rotary kiln temperature, the BP-PID controller is designed in theory, and the neural network trainings and simulations in MATLAB are taken. Secondly, by using the top-down method in VHDL language, the modules of BP-PID controller which is the BP neural network forward transmission module, the error back propagation module, and the weigh and threshold adjustment module and so on are all implemented on FPGA chip. Eventually the simulations of program in Quartus are given in this paper. The simulation results show that this design is reasonable, the hardware implementation is correct, so it can create the conditions for a wide range of applications of hardware intelligent algorithm in the field of industrial. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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MDE-based FPGA physical design: Fast model-driven prototyping with Smalltalk 11

MDE-based FPGA physical design: Fast model-driven prototypin...

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3rd international Workshop on Smalltalk Technologies 2011, IWST'11

作者： Teodorov, Ciprian Lagadec, Loïc Lab-STICC MOCS CNRS UMR 3192 France

ISBN: (纸本)9781450310505

The integrated circuit industry continues to progress rapidly deepening the gap in between the technological break-throughs and the electronic design automation industry. This gap is even more problematic in the context of physical design, the last automation level between applications and the technology. The challenges of meeting the physical and performance constraints necessitate innovation at the algorithmic level, and at the methodological level. This study presents a methodological approach to physical design automation relying on model-driven engineering. Relying on the flexibility, and adaptability of the Smalltalk environment we propose an agile framework enabling fast physical design tool-flow prototyping. We illustrate our approach by using the Madeo FPGA toolkit as a legacy codebase that is incrementally changed to adopt this modeldriven development strategy. Some pragmatic achievements are presented to illustrate the principal axes of this approach: algorithmic improvements through plug-and-play routines, domain-model extension for emerging technologies, as well as model evolution toward a meta-described environment. Copyright © 2011 acm.

关键词： field programmable gate arrays (FPGA)

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Low energy switch block for FPGAs

Low energy switch block for FPGAs

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proceedings - 17th international Conference on VLSI Design, Concurrently with the 3rd international Conference on Embedded Systems Design

作者： Krishnan, Rohini De Gyvez, Jose Pineda Digital Design and Test Group Philips Research Laboratories Eindhoven

We propose a new energy efficient method of designing switch blocks inside FPGAs using novel variations of the Dual Threshold CMOS (DTMOS) based switches instead of the conventional NMOS pass transistor or tri-state buffer based switches. By intelligently sharing the extra transistor needed for using DTMOS based switches, the area overhead is kept to a minimum. Sleep transistors are used to reduce sub-threshold leakage. Using our new, novel design, we obtain a 16% improvement in the power-delay product during the active mode per switch and a factor of 20 improvement in the stand-by mode, over conventional approaches. Extensive simulation results over benchmark circuits in CMOS 0.13μ are presented to illustrate the superiority of the proposed techniques. Since the proposed techniques target the switches and multiplexers which are present in large numbers on FPGAs, the overall improvement in the power-delay product is significant for an application implemented on a FPGA having the proposed features.

关键词： field programmable gate arrays

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An Accelerated Prototype with Movidius Neural Compute Stick for Real-Time Object Detection 3

An Accelerated Prototype with Movidius Neural Compute Stick ...

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3rd international symposium on Devices, Circuits and Systems, ISDCS 2020

作者： Kaarmukilan, S.P. Hazarika, Anakhi Amal Thomas, K. Poddar, Soumyajit Rahaman, Hafizur Indian Institute of Information Technology Guwahati Dept. of Electronics and Communication Engineering Guwahati India Indian Institute of Engineering Science and Technology Dept.of Information Technology Shibpur India

ISBN: (纸本)9781728165646

Object detection and recognition in realtime is the key task in many computer vision applications such as security surveillance, medical diagnosis, automated vehicle systems, etc. Now-a-days many deep learning techniques, especially convolutional neural networks (CNN) is widely used for real-time image detection and classification. The development of CNN models boosts the accuracy of object detection. However, the complex and data-intensive processing slows down the performance while implemented on hardware. This paper presents a low-powered, portable prototype on Xilinx PYNQ Z2 board with Movidius neural compute stick (NCS) that accelerates the object detection in real-time. Also, the proposed prototype utilized You Only Look Once (YOLO) approach for object detection. Frames per second (FPS), computation time and the probability of object recognition are the parameters considered to evaluate the performance of the proposed prototype and outperform the existing models. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Early stage power management for 3D FPGAs considering hierarchical routing resources 13

Early stage power management for 3D FPGAs considering hierar...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Nunna, Krishna Chaitanya Mehdipour, Farhad Murakami, Kazuaki Department of Advanced Informatics Kyushu University 3-8-33-309 Momochi Sawara-ku Fukuoka 814-0001 Japan E-JUST Center Kyushu University 3-8-33-305 Momochi Sawara-ku Fukuoka 814-0001 Japan Department of Advanced Informatics Kyushu University 744 Motooka Nishi-ku Fukuoka 819-0395 Japan

ISBN: (纸本)9781450319027

Designing for low power consumption demands power-efficient devices and good design practices to leverage the architectural features without compromising performance. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. In this paper, we are proposing a methodology for evaluating the power in three-dimensional field-programmable gate arrays (3D FPGAs) at an early stage of the design cycle namely at the partitioning step and making it a power-aware stage. As a part of the work, we also estimate the routing resources needed for the power evaluation. Our estimated power values are compared against the values obtained from a 3D place and route tool, TPR along with the added power calculations, which is demonstrating acceptable accuracy. Our results show that there is a scope for achieving desired distribution of power among the layers well before the placement with reasonable deviation in estimation and proves that our methodology is providing opportunity for power management at earlier stages of the design flow. © 2013 acm.

关键词： Power management

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High-Energy Physics on DECPeRLe-1 programmable Active Memory

High-Energy Physics on DECPeRLe-1 Programmable Active Memory

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： L. Moll J. Vuillemin P. Boucard Supérieure des Télécommunications Paris France Pôle Universitaire Léonard-de-Vinci La Defense France Matra-Harris Semiconductors Saint-Quentin-en-Yvelines France

The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (rd-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

关键词： Physics field programmable gate arrays

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On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

On Nominal Delay Minimization in LUT-Based FPGA Technology M...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： J. Cong Yuzheng Ding Computer Science Department UCLA Los Angeles CA USA

We study the nominal delay minimization problemin LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3, and remains NP-hard for duplication-free mapping and tree-based mapping for K ≥ 5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.

关键词： field programmable gate arrays Polynomials Delay estimation Table lookup Vegetation mapping Delay effects Minimization programmable logic arrays Computer networks Routing

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Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+

Bridging parallel and reconfigurable computing with multilev...

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3rd international Workshop on High-Performance Reconfigurable Computing Technology and Applications, HPRCTA'09, held in Conjunction with SC09

作者： Aggarwal, V. George, A. Yalamanchili, K. Yoon, C. Lam, H. Stitt, G. ECE Department University of Florida Gainesville FL 32611-6200 United States

ISBN: (纸本)9781605587219

Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such systems have demonstrated superior performance and reduced energy consumption versus their traditional counterparts based on microprocessors. However, most of such work has been limited to small system sizes. Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable HPC systems. In this paper, we introduce and investigate a novel programming model based on Partitioned Global Address Space (PGAS), which simplifies development of parallel applications for such systems. The new multilevel PGAS programming model captures the unique characteristics of these systems, such as the existence of multiple levels of memory hierarchy and heterogeneous computation resources. To evaluate this multilevel PGAS model, we extend and adapt the SHMEM programming language to become what we call SHMEM+, the first known SHMEM library enabling coordination between FPGAs and CPUs in a reconfigurable, heterogeneous HPC system. Our design of SHMEM+ is highly portable and provides peak communication bandwidth comparable to vendor-proprietary versions of SHMEM. In addition, applications designed with SHMEM+ yield improved developer productivity compared to current methods of multi-device RC design and achieve a high degree of portability. Copyright © 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Trigger Based on the Artificial Neural Network implemented in the Cyclone V FPGA for a Detection of Neutrino-Origin Showers in the Pierre Auger surface detector

Trigger Based on the Artificial Neural Network implemented i...

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3rd international Conference on Innovative Network Systems and Applications (iNetSApp) held in conjunction with Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Szadkowski, Zbigniew Glas, Dariusz Pytel, Krzysztof Univ Lodz Dept Phys & Appl Informat Fac High Energy Astrophys PL-90131 Lodz Poland Univ Lodz Dept Phys & Appl Informat Fac Informat PL-90236 Lodz Poland

ISBN: (纸本)9788360810668

Observations of ultra-high energy neutrinos became a priority in experimental astroparticle physics. Up to now, the Pierre Auger Observatory did not find any candidate on a neutrino event. This imposes competitive limits to the diffuse flux of ultra-high energy neutrinos in the EeV range and above. The prototype Front-End boards for Auger-Beyond-2015 with Cyclone (R) V E can test the neural network algorithm in real pampas conditions in 2015. Showers for muon and tau neutrino initiating particles on various altitudes, angles and energies were simulated in CORSIKA and OffLine platforms giving pattern of ADC traces in Auger water Cherenkov detectors. The 3-layer 12-10-1 neural network was taught in MATLAB by simulated ADC traces according the Levenberg -Marquardt algorithm. New sophisticated trigger implemented in Cyclone (R) V E FPGAs with large amount of DSP blocks, embedded memory running with 120 - 160 MHz sampling may support to discover neutrino events in the Pierre Auger Observatory.

关键词： field programmable gate arrays (FPGA)

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