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HGA: A Hardware-Based Genetic Algorithm

HGA: A Hardware-Based Genetic Algorithm

引用

proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： S.D. Scott A. Samal S. Seth Department of Computer Science Washington University Saint Louis MO USA Department of Computer Science and Engineering University of Nebraska Lincoln Lincolnshire NE USA

A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2-3 orders of magnitude faster than the software-based GA.

关键词： Genetic algorithms field programmable gate arrays Hardware Software prototyping Robustness Problem-solving Engines Scalability Coprocessors Design optimization

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Keynote 1 NoCs: It is about the memory and the programming model

Keynote 1 NoCs: It is about the memory and the programming m...

引用

international symposium on Networks-on-Chip (NOCS)

作者： Ivo Bolsens Xilinx Corp. USA

CPUs are multicore (and multi-cache) supported by a coherent, global, shared memory model. FPGAs offer a vast number of distributed programmable function blocks and distributed memory blocks across distributed memory spaces. This presentation will discuss a hybrid computing architecture that unifies the development of applications for a combined CPU-FPGA platform. The proposed programming model is based on message passing (MPI) and distributed memory. NoCs are at the heart of the hybrid platform managing the control and data flows. NoCs are implemented through shared memory buffers on the CPU portion of the hybrid computing platform. On parallel hardware, NoCs are implemented as application-specific point-to-point networks exploiting the abundant routing and switching resources of the FPGA. NoCs enable application-specific memory models while keeping with standard, familiar programming models such as MPI.

关键词： Network-on-a-chip field programmable gate arrays Hardware Digital signal processing Strontium Multicore processing Computer architecture Message passing Heart Central Processing Unit

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Design of tomato color sorting multi-channel real-time data acquisition and processing system based on FPGA

Design of tomato color sorting multi-channel real-time data ...

引用

作者： Ruoyu, Zhang Za, Kan Yinlan, Jiang Machinery and Electricity Engineering College Shihezi University Shihezi China

ISBN: (纸本)9780769543604

In order to meet the tomato color sorting system with the requirements of multi-channel data acquisition and real-time processing, []firstly, a multi-channel color digital acquisition and processing technique program based on FPGA were proposed. Then, a multi-channel data acquisition and real-time parallel processing system was built. The RGB color sensors were slected as detection components and the FPGA chip EP1C3T144C8 was slected as a core of data acquisition and processing. Meanwhile, ports of signal acquisition and the solenoid valve control were adopted a two-way analog switch HC4051 for saving I/O ports of FPGA. Thirdly, under the modular design and module reuse principles, we developed all modules with VHDL Language in QuartusII development environment. Finally, RTL and time sequence simulation for the system were done. The results showed that the connections between the modules accord with control logics. [accorded] The performance of system time sequencev are good, which can meet with the requirements of real-time processing of tomato color sorting. On these bases, we also conducted a tomato sorting test verification. The results showed that the average accuracy of sorting is 98.70 and coefficient of variation is 0.01. This results can meet requirements of production. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Welcoming message from the 2017 3rd ICST chairman

Welcoming message from the 2017 3rd ICST chairman

引用

international Conference on Science and Technology-Computer (ICST)

作者： Jumina State Key Lab of Synthetical Automation for Process Industries Northeastern University Shenyang Liaoning China College of Information and Engineering Shenyang University of Chemical Technology Shenyang Liaoning China

ISBN: (纸本)9781538618752

The 2017 3 rd international Conference on Science and Technology was held as a part of the Universitas Gadjah Mada Annual Scientific Conference (UASC) consisting four major events: international Conference on Science and Technology (ICST), international Conference on Tropical Agriculture (ICTA), international Conference on Health Sciences (ICHS), and international Conference on Southeast Asia Studies (ICSEAS). The 2017 3 rd international Conference on Science and Technology consisted of five symposia, namely the 5 th Annual Network on Natural and Unnatural Material symposium (ANNUM 5), 2 nd Computer symposium, 2 nd Geomaritime symposium, 1 st OMICS symposium, and 1 st Infrastructure Technology symposium. Accepted papers of the conference would be published in journals and proceedings indexed by Scopus, EBSCO or DOAJ, among others are the Indonesian Journal of Chemistry, Indonesian Journal of Geography, Indonesian Journal of Biotechnology, or IEEEXplore Digital Library.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Simple and fast fractal image compression for VLSI circuits

Simple and fast fractal image compression for VLSI circuits

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international symposium on Image and Signal Processing and Analysis

作者： A. Martinez-Ramirez A. Diaz-Sanchez M. Linares-Aranda J. Vega-Pineda Optics and Electronics INAOE National Institute of Astrophysics Mexico ITCh Technological Institute of Chihuahua Mexico

Nowadays fractal image coding is performed by several methods focused to reduce the number of comparisons. This work describes a simple and fast method of fractal image compression for applications in mobile communications. The method uses a quadtree scheme on multiple levels of image resolution and the fractal coding is applied taking advantage of the multiresolution decomposition. The method uses a simple scheme of blocks classification into each resolution level on a pyramidal decomposition according to size and the intensity variation level of every block. The simplicity and regularity of the method make it suitable to be implemented on programmable logic devices, such as FPGAs, or in custom VLSI integrated circuits. The method can be implemented in parallel, saving up to three orders in the number of necessary operations to codify the image, reducing the asymmetry of the coding time compared with the decoding time.

关键词： Fractals Image coding Very large scale integration Circuits Image resolution Focusing Mobile communication programmable logic devices field programmable gate arrays Decoding

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Single chip FPGA realization of a 2D multicomponent wavelet transform

Single chip FPGA realization of a 2D multicomponent wavelet ...

引用

international symposium on Image and Signal Processing and Analysis

作者： O. Venard R. Lionti L. Chra ESYCOM-ESIEE (Équipe Système de Communication) Noisy le grand France CEA LETI/DSIS Grenoble France

In this paper we describe a 2D wavelet transform (WT) implementation intended for color image compression. The proposed implementation handles the data stream on the YUV color space thanks to a multicomponent approach of the wavelet transform. The 2D WT is conducted in a separable manner by means of the 5-3 biorthogonal filters. This leads to a multiplier-less and low-latency on-line running computation, realization of a 2D multicomponent forward and inverse discrete wavelet transform (DWT) on a single FPGA chip.

关键词： field programmable gate arrays Wavelet transforms Discrete wavelet transforms Image coding Streaming media Video compression Space technology Discrete cosine transforms Transform coding Codecs

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Web-based embedded control platform

Web-based embedded control platform

引用

IEEE international symposium on Signal Processing and Information Technology (ISSPIT)

作者： Zhe Lou J. Pletinckx S. Verschuere Xing-Zhi Qiu J. Vandewege INTEC-design Ghent University Ghent Belgium

Many electrical instruments are provided with Internet connection, which is mostly used for non-real time operation, e.g. file transferring. However, the real-time controlling and/or monitoring are getting more and more attention nowadays. In this paper, a Web-based embedded control platform (WECP) that is used for real-time operation is depicted. This embedded control platform mainly consists of digital signal processors (DSP) and field-programmable gate array (FPGA) chips. The DSP processors offer many standard industrial interfaces that can be used to connect with the other personal computers (PCs) and instruments. It is the main processor that handles digital signal processing, monitoring, and control of the whole system. The FPGA chips are mainly for fast data transmission and reception, which are directly connected to the analog front-ends (AFE) and instruments. Furthermore, this control platform offers an Internet link, through which the customers can control the DSP and the FPGA via a PC on the Internet. The programmability of both DSP processors and FPGA chips makes this control platform quite flexible, which greatly reduces the development cost. The experiment results show that the WECP is suitable for real-time operations.

关键词： Digital signal processing chips field programmable gate arrays Instruments Internet Monitoring Digital signal processors Computer industry Electrical equipment industry Microcomputers Personal communication networks

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High-energy physics on DECPeRLe-1 programmable active memory 95

High-energy physics on DECPeRLe-1 programmable active memory

引用

proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Laurent Moll Jean Vuillemin Philippe Boucard Ecole Nationale Supérieure des Télécommunications Paris France Pôle Universitaire Léonard-de-Vinci La Défense France Matra-Harris Semiconductors Saint-Quentin-en-Yvelines France

ISBN: (纸本)9780897917438

The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (rd-11) group and DEC-PRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1 [2]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

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HGA: a hardware-based genetic algorithm 95

HGA: a hardware-based genetic algorithm

引用

proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Stephen D. Scott Ashok Samal Shared Seth Dept. of Computer Science Washington University St. Louis MO Dept. of Computer Science and Engineering University of Nebraska-Lincoln Lincoln NE

ISBN: (纸本)9780897917438

A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2–3 orders of magnitude faster than the software-based GA.

关键词： function optimization performance evaluation performance acceleration parallel genetic algorithms field programmable gate arrays

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Towards an efficient hardware implementation of recurrent neural network based multiuser detection

Towards an efficient hardware implementation of recurrent ne...

引用

IEEE international symposium on Spread Spectrum Techniques and Applications

作者： W.G. Teich A. Engelhart W. Schlecker R. Gessler H.-J. Pfleiderer Information Technology University of Ulm (EBS) Ulm Germany Microelectronics Department University of Ulm (EBS) Ulm Germany

Code division multiple access (CDMA) will be an important part of 3rd generation mobile communication systems worldwide. Besides its many advantages, CDMA has the disadvantage that CDMA systems are interference limited. However, this limitation can be overcome by proper multiuser detection (MUD). We propose a MUD based on recurrent neural networks (RNN). This algorithm provides a performance which is close to the optimum MUD, while keeping the computational complexity low. Furthermore, the regular structure of the algorithm facilitates a hardware (HW) implementation utilizing distributed computation. The HW platform we target at are field programmable gate arrays (FPGA). Compared to application specific integrated circuits, FPGAs allow a much faster and more flexible hardware implementation. We have implemented the algorithm with a fixed point arithmetic and investigated the minimum number of binary digits required so that the performance of the algorithm does not degrade substantially. Furthermore an efficient implementation of the tanh nonlinearity is presented.

关键词： Hardware Multiaccess communication Multiuser detection field programmable gate arrays Recurrent neural networks 3G mobile communication Interference Computational complexity Distributed computing Application specific integrated circuits

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