The proceedings contain 239 papers. The topics discussed include: exploration of timing and higher-energy attacks on quantum random access memory;fortifying the NAND flash supply chain with innovative security primiti...
ISBN:
(纸本)9798400710773
The proceedings contain 239 papers. The topics discussed include: exploration of timing and higher-energy attacks on quantum random access memory;fortifying the NAND flash supply chain with innovative security primitives;optimizing supply chain management using permissioned blockchains;systematic use of random self-reducibility in cryptographic code against physical attacks;enhancing privacy-preserving computing with optimized CKKS encryption: a hardware acceleration approach;a hypergraph partitioner utilizing a novel graph generative model;TopoOrderPart: a multi-level scheduling-driven partitioning framework for processor-based emulation;modern fixed-outline floorplanning with rectilinear soft modules;JigsawPlanner: jigsaw-like floorplanner for eliminating whitespace and overlap among complex rectilinear modules;and an effective analytical placement approach to handle fence region constraint.
The proceedings contains 109 papers from the 1998 ieeeinternationalconference on computer-aideddesign. Topics discussed include: circuit simulation;layout and logic synthesis;dynamic system synthesis;design for tes...
详细信息
The proceedings contains 109 papers from the 1998 ieeeinternationalconference on computer-aideddesign. Topics discussed include: circuit simulation;layout and logic synthesis;dynamic system synthesis;design for testability;reduced order modeling;combinatorial logic synthesis;sequential circuit testing;numerical techniques for simulation and extraction;intellectual property protection;estimating noise in radio frequency systems;noise in digital systems;pass transistor and domino logic synthesis;floorplanning;test generation techniques;analog circuit synthesis;timing optimization in sequential synthesis;high-level synthesis;sequential verificational;memory and interfaces synthesis;and power estimation.
The proceedings contains 101 papers from the 1996 internationalconference on computeraideddesign. Topics discussed include: technology mapping;interconnect characterization and analysis;high performance routing syn...
详细信息
The proceedings contains 101 papers from the 1996 internationalconference on computeraideddesign. Topics discussed include: technology mapping;interconnect characterization and analysis;high performance routing synthesis;sequential circuit testing;formal verification;system design synthesis and compilation;timing analysis;high level design;power and performance in high level synthesis;high performance circuit optimization;circuit partitioning;automatic test pattern generation (ATPG);embedded applications;implication-based logic synthesis;advance numerical simulation techniques;robust routing;yield and technology modeling;power and timing analysis;verification and fault tolerance;and analog CAD and methodology.
The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aideddesign. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimat...
详细信息
The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aideddesign. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimation of power bounds;interconnect modeling;multi-level synthesis and covering problems;code generation and processor design;high level power prediction and reduction;noise analysis and modeling;timing analysis;microelectromechanical systems;high performance digital circuits;sequential circuit optimization;advanced scheduling techniques;clock design and optimization;circuit simulation and optimization;circuit partitioning;fault simulation and diagnosis;logic synthesis;real time systems;and interconnect optimization.
The proceedings contain 164 papers. The topics discussed include: fine-granular computation and data layout reorganization for improving locality;physics-aware differentiable discrete codesign for diffractive optical ...
ISBN:
(纸本)9781450392174
The proceedings contain 164 papers. The topics discussed include: fine-granular computation and data layout reorganization for improving locality;physics-aware differentiable discrete codesign for diffractive optical neural networks;big-little chiplets for in-memory acceleration of DNNs: a scalable heterogeneous architecture;false data injection attacks on sensor systems;stochastic mixed-signal circuit design for in-sensor privacy;sensor security: current progress, research challenges, and future roadmap;design and technology co-optimization utilizing multi-bit flip-flop cells;transitive closure graph-based warpage-aware floorplanning for package designs;SODA synthesizer: an open-source, multi-level, modular, extensible compiler from high-level frameworks to silicon;a scalable methodology for agile chip development with open-source hardware components;a novel semi-analytical approach for fast electromigration stress analysis in multi-segment interconnects;and sub-resolution assist feature generation with reinforcement learning and transfer learning.
The proceedings contain 152 papers. The topics discussed include: routability-driven global placer target on removing global and local congestion for VLSI designs;acceleration method for learning fine-layered optical ...
ISBN:
(纸本)9781665445078
The proceedings contain 152 papers. The topics discussed include: routability-driven global placer target on removing global and local congestion for VLSI designs;acceleration method for learning fine-layered optical neural networks;an optimal algorithm for splitter and buffer insertion in adiabatic quantum-flux-parametron circuits;lower voltage for higher security: using voltage overscaling to secure deep neural networks;demystifying the characteristics of high bandwidth memory for real-time systems;a convergence monitoring method for DNN training of on-device task adaptation;a unified framework for layout pattern analysis with deep causal estimation;and analytical modeling of transient electromigration stress based on boundary reflections.
The proceedings contain 200 papers. The topics discussed include: Meltrix: a RRAM-based polymorphic architecture enhanced by function synthesis;PDNSig: identifying multi-tenant cloud FPGAs with power distribution netw...
ISBN:
(纸本)9798350315592
The proceedings contain 200 papers. The topics discussed include: Meltrix: a RRAM-based polymorphic architecture enhanced by function synthesis;PDNSig: identifying multi-tenant cloud FPGAs with power distribution network-based signatures;HAPIC: a scalable, lightweight and reactive cache for persistent-memory-based index;floorplanning for embedded multi-die interconnect bridge packages;CircuitOps: an ML infrastructure enabling generative AI for VLSI circuit optimization;FLEX : introducing flexible execution on CGRA with spatio-temporal vector dataflow;bespoke approximation of multiplication-accumulation and activation targeting printed multilayer perceptrons;side channel-assisted inference attacks on machine learning-based ECG classification;path-based processing using in-memory systolic arrays for accelerating data-intensive applications;and clock aware low power placement.
The proceedings contain 121 papers. The topics discussed include: a scalable decision procedure for fixed-width bit-vectors;generation of optimal obstacle-avoiding rectilinear steiner minimum tree;obstacle-avoiding re...
ISBN:
(纸本)9781605588001
The proceedings contain 121 papers. The topics discussed include: a scalable decision procedure for fixed-width bit-vectors;generation of optimal obstacle-avoiding rectilinear steiner minimum tree;obstacle-avoiding rectilinear steiner tree construction based on steiner point selection;how to consider shorts and guarantee yield rate improvement for redundant wire insertion;power-switch routing for coarse-grain MTCMOS technologies;scheduling with soft constraints;REMiS: run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set;resilient circuits - enabling energy-efficient performance and reliability;resilience in computer systems and networks;scan power reduction in linear test data compression scheme;compacting test vector sets via strategic use of implications;and pre-ATPG path selection for near optimal post-ATPG process space coverage.
暂无评论