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检索条件"任意字段=Proceedings of the 1995 IEEE Multi-Chip Module Conference"

共 259 条记录，以下是1-10 订阅

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multi-chip Stacked Memory module Development using chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications 74

Multi-Chip Stacked Memory Module Development using Chip to W...

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ieee 74th Electronic Components and Technology conference (ECTC)

作者： Sekhar, Vasarla Nagendra Kumar, Mishra Dileep Tippabhotla, Sasi Kumar Rao, B. S. S. Chandra Daniel, Ismael Cereno Chong, Ser Choong Rao, Vempati Srinivasa ASTAR Inst Microelect IME 2 Fusionopolis WayInnovis 08-02 Singapore 138634 Singapore

ISBN: (纸本)9798350375985;9798350375992

The present study focuses on multi-chip stacked memory module development, and it encompasses a comprehensive overview of critical aspects, key learnings, encountered challenges, and the corresponding mitigation strategies. It initiates the formulation of test vehicle designs and progresses through mechanical simulations, wafer fabrication, and meticulous materials selection. It delves into the complexities of chip-to-wafer (C2W) hybrid bonding and assembly processes for hybrid bonding module development. The test vehicle design is tailored to accommodate a substrate along with two logic and memory stacked test chips. Extensive finite element analysis (FEA) simulations are conducted to comprehend and enhance the integrity of bonded dielectric layers and Cu pads, considering diverse designs, materials, and process parameters of the C2W-HB processes. For test chip stacking, chip design, dielectric materials selection, wafer fabrication methodology, chip warpage, and hybrid bonding approach play a critical role. The process integration, dielectric stack, and dielectric deposition recipes have been fine-tuned to limit the thin memory chip warpage to less than 60 mu m, ensuring successful chip stacking and hybrid bonding. Several fabrication processes and modules have been optimized to fabricate memory wafers with double-side hybrid bonding pads and TSV structures using low-temperature dielectric materials on the backside. Following C2W hybrid bonding and molding, under-bump metallization (UBM) fabrication is established on the substrate wafer backside for electrical testing and board-level assembly purposes. Electrical testing outcomes and yields at the UBM match those obtained from wafer front-side testing.

关键词： chip-to-wafer hybrid bonding multi-chip stacking finite element analysis thin wafer handling process challenges mitigation plans

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Barre Chord: Efficient Virtual Memory Translation for multi-chip-module GPUs 51

Barre Chord: Efficient Virtual Memory Translation for Multi-...

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ACM/ieee 51st Annual International Symposium on Computer Architecture (ISCA)

作者： Feng, Yuan Na, Seonjin Kim, Hyesoon Jeon, Hyeran Univ Calif Merced CA 95343 USA Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9798350326598;9798350326581

With the advancement of processor packaging technology and the looming end of Moore's law, multi-chip-module (MCM) GPUs become a promising architecture to continue the performance scaling. However, due to the increasing concurrency, it is challenging to achieve scalable performance. In this study, we show that the limited parallelism in IOMMU is one of the critical bottlenecks and propose Barre Chord to fundamentally reduce the translation loads. By leveraging the unique GPU execution model and page mapping on MCM-GPUs, Barre translates virtual addresses in a unit of coalescing group. Once one page is translated, all the other pages within the same coalescing group can be translated with simple calculations without page table walks. Full Barre (F-Barre) further reduces translations by enabling intra-MCM translation through coalescing information sharing across GPU chiplets and contiguity-aware coalescing group expansion. With the combination of Barre and F-Barre, the Barre Chord outperforms state-of-the-art solutions by an average of 1.36x (2.09x with coalescing group expansion) with negligible area overhead (4.22% of a GPU L2 TLB).

关键词： Program processors

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New power delivery network(PDN) approach for extremely large FC-BGA with organic substrate based on over 1mm-thick core 74

New power delivery network(PDN) approach for extremely large...

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ieee 74th Electronic Components and Technology conference (ECTC)

作者： Hwang, Kyojin Jung, Woobin Kim, Junghwa Lee, Heeseok Pak, Junso Hwang, Jisoo Samsung Elect Co Ltd SLSI Business Hwaseong South Korea

ISBN: (纸本)9798350375985;9798350375992

In this paper, the authors propose two solutions for thick embedding capacitor that can be embedded in extremely large Flip chip Ball Grid Array (FC-BGA) Package (PKG) using a Thick Core Substrate (TCS) with thickness of more than 1 mm. Firstly, the authors propose an embedded Capacitor module (eCM) solution. In this solution, it is possible to package multiple capacitors into single capacitor module. To do that, mount multiple multi-Layer Ceramic Capacitor (MLCC) on a substrate with external electrodes made of copper (Cu) and then perform molding. This solution is suitable for embedding capacitors into TCS because it allows control of thickness while packaging multiple capacitors. It also enables implementation of larger capacitance, and customization of size and capacitance according to System on chip (SoC) requirements through the combinations of internal capacitors. Furthermore, it is effective for improving Power Delivery Network (PDN) performance as it allows to directly connect capacitance to the desired IP blocks according to SoC package design. Secondly, the authors propose Through Silicon Via (TSV)-based Stacked Silicon Capacitor (SSC). As presented by authors' another paper [1], TSV-based SSC can be used for embedded Capacitor (eCAP) with TCS. A SSC is created by producing silicon capacitor wafers with applied TSV and stacking two identical wafers through wafer-to-wafer bonding. Repeat this process N times to fabricate SSC that consists of N silicon capacitors. SSC provides lower Equivalent Series Inductance (ESL) characteristics and N times higher capacitance compared to conventional silicon capacitors. SSC can be manufactured with the same thickness as that of the core layer of TCS. Additionally, SSC makes shortcut PDN design between die bumps and PKG balls through TSV, which further enhances PDN performance. This paper provides a comparative study on PDNs that are designed using Die Side Capacitor (DSC) versus PDNs that are designed using eCM and TSV-b

关键词： Embedding capacitor module Stacked silicon capacitor TSV silicon capacitor Thick core based large package

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High Power Thermal Test Vehicle with 2-Phase Cooling for AI Datacenters, 5G RAN, and EDGE Compute Nodes 74

High Power Thermal Test Vehicle with 2-Phase Cooling for AI ...

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ieee 74th Electronic Components and Technology conference (ECTC)

作者： Liu, Yang Basavanhally, Nagesh Earnshaw, Mark Salamon, Todd Papazian, Rick Hu, Ting-Chen Cappuzzo, Mark Kopf, Rose Apigo, David Farah, Bob Faisal, Syed Roy, Rishav Nokia Bell Labs Murray Hill NJ 07974 USA

ISBN: (纸本)9798350375985;9798350375992

In this paper, we introduce the design and fabrication of a high-power thermal test vehicle (TTV) equipped with a two-phase cooling system, targeting improved thermal management in multi-chip modules (MCMs) for AI datacenters, 5G RAN, and EDGE compute nodes. With the rise in device integration and component power densities, conventional cooling methods fall short, prompting the need for innovative approaches to achieve efficient heat dissipation. The TTV utilizes advanced heterogeneous integration techniques on a low-temperature cofired ceramic (LTCC) substrate, designed to reliably dissipate over 1000 W of heat. This provides a robust platform for testing advanced two-phase cooling strategies to effectively remove heat from densely packed silicon dies, thus addressing the thermal challenges inherent in modern electronics. We elaborate on the fabrication of two variations of the TTV: the first comprising six X1 MCM modules, each measuring 25 mm x 38 mm, and the second a single X6 module measuring 76 mm x 76 mm, showcasing the robustness of the process. These TTVs are engineered to manage power dissipation of up to 1008 W, with logic chips experiencing background power densities of approximately 34 W/cm<^>2 and hotspots peaking at 400W/cm<^>2, while HBM stack chips exhibit a heat flux of 16 W/cm<^>2. The logic chips, measuring 20 mm x 20 mm, and the HBM stacks, measuring 10 mm x 10 mm, closely replicate the specifications of cutting-edge AI hardware. The importance of this work lies in its capacity to offer a scalable and dependable testing platform for advanced thermal management strategies in high-performance computing. By leveraging two-phase cooling, it paves the way toward more reliable and efficient computing infrastructures, effectively addressing the challenges posed by high power and heat flux in contemporary electronic devices.

关键词： MCM multi-chip module two-phase cooling OHP Thermal Test Vehicle TTV

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A multi-module silicon-on-insulator chip assembly containing quantum dots and cryogenic radio-frequency readout electronics 31

A multi-module silicon-on-insulator chip assembly containing...

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31st conference on Electronics Circuits and Systems

作者： Ibberson, David J. Kirkman, James Morton, John J. L. Gonzalez-Zalba, M. Fernando Gomez-Saiz, Alberto Quatum Motion 9 Sterling Way London N7 9HJ England UCL London Ctr Nanotechnol London WC1H 0AH England

ISBN: (纸本)9798350377217;9798350377200

Quantum processing units will be modules of larger information processing systems containing also digital and analog electronics modules. Silicon-based quantum computing offers the enticing opportunity to manufacture all the modules using the same technology platform. Here, we present a cryogenic multi-module assembly for multiplexed readout of silicon quantum devices where all modules have been fabricated using the same fully-depleted silicon-on-insulator (FDSOI) CMOS process. The assembly is constituted by three chiplets: (i) a low-noise amplifier (LNA), (ii) a single-pole eight-throw switch (SP8T), and (iii) a silicon quantum dot (QD) array. We integrate the chiplets into modules and show respectively, (i) a peak gain over 35 dB with a 3-dB bandwidth from 709 MHz to 827 MHz and an average noise temperature of 6.2 K (minimum 4.2 K), (ii) an insertion loss smaller than 1.1 dB and a noise temperature less than 1.1 K over the 0-2 GHz range, and (iii) single-electron box (SEB) charge sensors. Finally, we combine all modules into a single demonstration showing time-domain radio-frequency multiplexing of two SEBs paving the way to an all-silicon quantum computing system.

关键词： Cryo-CMOS cryogenic low-noise amplifiers (LNA) quantum computing single-electron devices single-pole eight-throw switch (SP8T) time-division multiplexing

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SAC: Sharing-Aware Caching in multi-chip GPUs 23

SAC: Sharing-Aware Caching in Multi-Chip GPUs

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50th Annual International Symposium on Computer Architecture (ISCA)

作者： Zhang, Shiqing Naderan-Tahan, Mahmood Jahre, Magnus Eeckhout, Lieven Univ Ghent Ghent Belgium Norwegian Univ Sci & Technol NTNU Trondheim Norway

ISBN: (纸本)9798400700958

Bandwidth non-uniformity in multi-chip GPUs poses a major design challenge for its last-level cache (LLC) architecture. Whereas a memory-side LLC caches data from the local memory partition while being accessible by all chips, an SM-side LLC is private to a chip while caching data from all memory partitions. We find that some workloads prefer a memory-side LLC while others prefer an SM-side LLC, and this preference solely depends on which organization maximizes the effective LLC bandwidth. In contrast to prior work which optimizes bandwidth beyond the LLC, we make the observation that the effective bandwidth ahead of the LLC is critical to end-to-end application performance. We propose Sharing-Aware Caching (SAC) to adopt either a memory-side or SM-side LLC organization by dynamically reconfiguring the routing policies in the intra-chip interconnection network and LLC controllers. SAC is driven by a simple and lightweight analytical model that predicts the impact of data sharing across chips on the effective LLC bandwidth. SAC improves average performance by 76% and 12% (and up to 157% and 49%) compared to a memory-side and SM-side LLC, respectively. We demonstrate significant performance improvements across the design space and across workloads.

关键词： multi-socket GPU multi-chip-module (MCM) GPU Network-onchip (NoC) data sharing cache organization

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A High Power Density Gate Driver Integrated SiC multichip Power module with Lower Parasitic Inductance 2

A High Power Density Gate Driver Integrated SiC Multichip Po...

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2nd ieee International Power Electronics and Application Symposium, PEAS 2023

作者： Zeng, Chenhang Chen, Cai Kang, Yong School of Electrical and Electronic Engineering Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9798350313765

In applications such as multi-electric aircraft, there is an increasing demand for power modules that offer improved volume efficiency and integration. Integration of gate drivers and power semiconductors can reduce the volume of the entire system and reduce the parasitic inductance of the drive circuit, which called intelligent power module(IPM). Consequently, research on high-power intelligent power modules (IPMs) is crucial. However, existing high-power IPMs still suffer from issues such as large physical dimensions and undesirable parasitic inductance. This paper presents a novel approach to address these challenges by introducing a 800V/200A multi-chip parallel intelligent SiC power module with an integrated driver chip. By optimizing the layout of the power loop and the drive loop, a power loop inductance of 7nH and a drive loop inductance of 11.5nH are achieved. Additionally, the warpage of large-size direct bond copper (DBC) substrates is reduced by 36% through the optimization of copper layer thickness, achieving high power density, low parasitic inductance, and enhanced reliability. © 2023 ieee.

关键词： gate driver integrated high power density power module SiC

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Package Power Delivery Architecture for High Performance Computing Systems With a 1 kW IVR Operated in CCM-DCM Boundary Mode Condition 74

Package Power Delivery Architecture for High Performance Com...

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ieee 74th Electronic Components and Technology conference (ECTC)

作者： Khorasani, Ramin Rahimzadeh Li, Xingchen Kim, Joon Woo Murali, Prahalad Sharma, Rohit Swaminathan, Madhavan Penn State Univ Sch Elect Engn & Comp Sci University Pk PA 16802 USA Indian Inst Technol Ropar Dept Elect Engn Rupnagar 140001 India

ISBN: (纸本)9798350375985;9798350375992

This paper investigates a package power delivery architecture for high-performance computing (HPC), incorporating a novel modular multi-phase integrated voltage regulator (IVR). The 1-kW 48-12/1 V architecture integrates an efficient interleaved buck-derived converter at the continuous-discontinuous boundary condition, facilitating parallel-connected networks of embedded inductors to deliver hundreds of amperes per phase. Due to the increased duty cycle and zero switching losses provided for the high side switch, the converter's frequency can be further increased up to 50 MHz with 8 parallel phases and 100 MHz with 16 parallel phases for a 48/1 V, 1 kW architecture. A conceptual 3-D stacked architecture using stacked glass substrates with flip chip GaN switches and embedded inductors, and capacitors is presented, offering a high-density single-stage 48-12/1 V IVR for the next generation of data center applications.

关键词： 3-d stack heterogeneous integration integrated voltage regulator module (IVR) soft switching zero switching losses vertical power delivery embedded inductor

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multi-RF chip module through FOWLP 26

Multi-RF chip module through FOWLP

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26th Electronics Packaging Technology conference, EPTC 2024

作者： Boon, Serine Soh Siew Wee, David Ho Soon Yee, Chia Lai Jaafar, Norhanani Soh, Jacob Yao, Hsiao Hsiang Shan, Sharon Lim Pei Feng, Xu Kuan, Ong Poh Teck, Chan Kien 2 Fusionopolis Way Innovis #08-02 Singapore138634 Singapore MEDs Technologies Pte Ltd Singapore

ISBN: (纸本)9798331522001

This paper depicts the development of multiple Pseudomorphic high electron mobility transistor (pHEMT) semiconductors with AlGaAs/InGaAs/GaAs developed to realize high power and high-efficiency amplifiers for System-in-Package (SiP) modules. The developed Fan-out package measures 5.27mm X 7.15 mm X 0.15mm, based on the electrical simulation has anticipated gain of approximately 3-4dB, with power consumption © 2024 ieee.

关键词： System-in-package

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Analysis and Mitigation of Short Circuit Current in multichip Power module with Paralleled SiC MOSFETs 3

Analysis and Mitigation of Short Circuit Current in Multichi...

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3rd ieee International Power Electronics and Application conference and Exposition, PEAC 2022

作者： Zhang, Man Li, Helong Han, Lianglaing Zhao, Shuang Ding, Lijian Hefei University of Technology School of Electrical Engineering and Automation Hefei China

ISBN: (数字)9781665491419

ISBN: (纸本)9781665491419

In this paper, a new substrate layout is proposed in order to mitigate the short-circuit current imbalance of a typical multi-chip power module with paralleled SiC MOSFETs. Compared with the typical SiC power modules, the influence of common-source inductance mismatch on the current imbalance is effectively minimized in the proposed layout. Consequently, the current sharing performance of the paralleled SiC MOSFETs in the multi-chip power module is improved. The analyses are verified by simulation and experimental results, which further validate the effectiveness of this mitigating method. © 2022 ieee.

关键词： Silicon carbide

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