检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

599 篇 会议
30 篇 期刊文献

馆藏范围

629 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

511 篇 工学
- 469 篇 计算机科学与技术...
- 285 篇 软件工程
- 225 篇 电子科学与技术（可...
- 144 篇 电气工程
- 88 篇 信息与通信工程
- 35 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 26 篇 机械工程
- 15 篇 生物工程
- 13 篇 仪器科学与技术
- 9 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 材料科学与工程（可...
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 3 篇 农业工程
203 篇 理学
- 170 篇 数学
- 35 篇 物理学
- 19 篇 统计学（可授理学、...
- 16 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
54 篇 管理学
- 46 篇 管理科学与工程(可...
- 29 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学

主题

275 篇 field programmab...
172 篇 field programmab...
35 篇 signal processin...
35 篇 clocks
33 篇 modulation
33 篇 ofdm
33 篇 estimation
33 篇 filtration
30 篇 fpga
9 篇 table lookup
9 篇 routing
9 篇 systolic arrays
9 篇 switches
8 篇 field-programmab...
7 篇 fpgas
7 篇 optimization
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university
3 篇 state key lab of...
3 篇 computer science...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

622 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是121-130 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs 05

Analysis of yield loss due to random photolithographic defec...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Campregher, Nicola Cheung, Peter Y. K. Vasilko, Milan Constantinides, George A. Electrical and Electronic Engineering Imperial College London United Kingdom School of Design Engineering and Computing Bournemouth University United Kingdom

ISBN: (纸本)9781595930293

This paper presents an analysis of the potential yield loss in FPGA due to random defects in metal layers. A proven yield model is adapted to target the FPGA interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Automated synthesis for asynchronous FPGAs 05

Automated synthesis for asynchronous FPGAs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Peng, Song Fang, David Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States Advanced Microelectronics Department Sandia National Laboratories United States

ISBN: (纸本)9781595930293

Advanced Microelectronics Department at Sandia National Laboratories. We present an automatic logic synthesis method targeted for high-performance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Post-placement C-slow retiming for the xilinx virtex FPGA

Post-placement C-slow retiming for the xilinx virtex FPGA

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Weaver, Nicholas Markovskiy, Yury Patel, Yatish Wawrzynek, John UC Berkeley Berkeley CA United States

C-slow retiming is a process of automatically increasing the throughput of a design by enabling fine grained pipelining of problems with feedback loops. This transformation is especially appropriate when applied to FPGA designs because of the large number of available registers. To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs. Applying our tool to three benchmarks: AES encryption. Smith/Waterman sequence matching, and the LEON 1 synthesized microprocessor core, we were able to substantially increase the total throughput. For some parameters, throughput is effectively doubled.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Efficiently supporting fault-tolerance in FPGAs 98

Efficiently supporting fault-tolerance in FPGAs

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Lach, John Mangione-Smith, William H. Potkonjak, Miodrag UCLA EE Dep Los Angeles CA United States

ISBN: (纸本)9780897919784

While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

An iterative division algorithm for FPGAs 06

An iterative division algorithm for FPGAs

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Liu, Jianhua Chang, Michael Cheng, Chung-Kuan Computer Science and Engineering Department University of California San Diego 92093 United States

ISBN: (纸本)1595932925

Division is one of the most complicated and expensive arithmetic operations. Both clock frequency and operation delay are limited by the memory wall, even in LUT-based FPGA devices. To conquer the memory limitation, we propose a hybrid division algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms. The proposed algorithm boosts very-high radix division efficiently. The algorithm is multiplicative, and feasible for the modern FPGA devices with build-in multipliers. The algorithm is implemented in Altera StratixII FPGA devices and compared with the division IP core generated by Mega Wizard. The result shows that the PST algorithm has higher clock frequency, lower execution time and also lower power consumption. Copyright 2006 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

field programmable Port Extender (FPX) for distributed routing and queuing 00

Field Programmable Port Extender (FPX) for distributed routi...

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Lockwood, John W. Turner, Jon S. Taylor, David E. Washington Univ Saint Louis MO United States

ISBN: (纸本)9781581131932

field programmable gate arrays (FPGAs) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic. FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports. Logic on the FPX module is implemented with two FPGA devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second FPGA can be re-programmed dynamically via control cells sent over the network.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Highly pipelined asynchronous FPGAs

Highly pipelined asynchronous FPGAs

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States

We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can efficiently take advantage of this large amount of pipelining. Our FPGA, which does not use a clock to sequence computations, automatically "self-pipelines" its logic without the designer needing to be explicitly aware of all pipelining details. This property makes our FPGA ideal for throughput-intensive applications and we require minimal place and route support to achieve good performance. Benchmark circuits taken from both the asynchronous and clocked design communities yield throughputs in the neighborhood of 300-400 MHz in a TSMC 0.25μm process and 500-700 MHz in a TSMC 0.18μm process.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Memory-to-memory connection structures in FPGAs with embedded memory arrays 97

Memory-to-memory connection structures in FPGAs with embedde...

引用

proceedings of the 1997 acm 5th international symposium on field-programmable gate arrays, FPGA

作者： Wilton, Steven J.E. Rose, Jonathan Vranesic, Zvonko G. Univ of British Columbia Vancouver BC Canada

ISBN: (纸本)9780897918015

This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to multiple memory arrays are often difficult to route, and are often part of the critical path of circuit implementations. The memory-to-memory connection structure proposed in this paper allows for the efficient implementation of these nets, resulting in a reduction in memory access time of up to 25% and a slight improvement in routability.

关键词： Parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays 00

Heterogeneous technology mapping for FPGAs with dual-port em...

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Wilton, Steven J.E. Univ of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581131932

It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. This previous work has only considered single-port arrays. Many current FPGAs, however, contain dual-port arrays. In this paper we present an algorithm that maps logic to these dual-port arrays. Our algorithm can either optimize area with no regard for circuit speed, or optimize area under the constraint that the combinational depth of the circuit does not increase. Experimental results show that, on average, our algorithm packs between 29% and 35% more logic than an algorithm that targets single-port arrays. We also show, however, that even with this algorithm, dual-port arrays are still not as area-efficient as single-port arrays when implementing logic.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

FPCNA: A field programmable carbon nanotube array

FPCNA: A field programmable carbon nanotube array

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Dong, Chen Chilstedt, Scott Chen, Deming Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign Urbana-Champaign United States

ISBN: (纸本)9781605584102

Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architecture known as FPCNA. We define novel CNT and nanoswitch based components and characterize these components considering nanospecific process variations, including the variation caused by the random mixture of metallic and semiconducting CNTs. To evaluate the architecture, we develop a variation-aware physicaldesign flow which can handle both Gaussian and non-Gaussian random variables using variation-aware placement and routing. When FPCNA is evaluated with this CAD flow, we see a 2.67 performance gain over a baseline CMOS FPGA at the same technology node (at a 95% performance yield). In addition, FPCNA offers a 4.5 footprint reduction compared to the baseline FPGA. These results demonstrate the potential of using CNTs and nanoswitches to build high performance FPGA circuits. Copyright 2009 acm.

关键词： Carbon nanotubes

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共63页 << < 9 10 11 12 13 14 15 16 17 18 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：