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Design of programmable interconnect for sublithographic programmable logic arrays 05

Design of programmable interconnect for sublithographic prog...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： DeHon, André Dept. of CS 256-80 California Institute of Technology Pasadena CA 91125 United States

ISBN: (纸本)9781595930293

Sublithographic programmable Logic arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional lithographic patterning, we show how modestsized PLA logic blocks, which are efficient for implementing logic, can be organized into a segmented, Manhattan mesh interconnection scheme. The resulting programmable architecture has a macro-scale view which is reminiscent of lithographic FPGA and CPLD designs despite the fact that the low-level, sublithographic fabrication techniques used are much more highly constrained than conventional lithography and are prone to high defect rates. Using the Toronto 20 benchmark set, we begin to explore the design space for these sublithographic architectures and show that they may allow us to exploit nanowire building blocks to reach one to two orders of magnitude greater density than 22nm CMOS lithography. Copyright 2005 acm.

关键词： programmable logic controllers

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Figaro: An automatic tool flow for designs with dynamic reconfiguration

Figaro: An automatic tool flow for designs with dynamic reco...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Nasi, Kelly Daněk, Martin Karoubalis, Theodoras Pohl, Zdeněk Atmel Hellas S.A. Papazachariou 48 GR 17342 Ag. Dimitros Athens Greece Inst. of Information Theory and Automation Czech Academy of Sciences Pod vodarenskou vezi 4 182 08 Praha 8 Czech Republic

Although runtime dynamic reconfiguration of the FPGA devices has been an issue of the last decade, it has yet to achieve general recognition by the design community. The reasons for this are clear;there exists no straightforward design methodology, and the partitioning and CAD tool support is poor. This paper presents general concepts implemented in a placement and routing tool that provides an environment where designs that are partially and dynamically reconfigurable can be processed in order to be implemented on FPGAs that support this technology, such as the Armel AT40K and AT94K series. The function of the tool is demonstrated on a simple real-world example.

关键词： field programmable gate arrays

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Design of FPGAs with area I/O for field programmable MCM 95

Design of FPGAs with area I/O for field programmable MCM

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proceedings of the 1995 acm 3rd international symposium on field-programmable gate arrays

作者： Maheshwari, Vijayshri Darnauer, Joel Ramirez, John Dai, Wayne Wei-Ming UC Santa Cruz Santa Cruz CA United States

ISBN: (纸本)9780897917438

Area-IO provide a way to eliminate the IO bottleneck of field programmable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and the propensity of logic to demand it. Whether the incorporation of area IO into FPLD architectures has undesirable side effects is a question that has not yet been answered. In this paper, we examine the architectural impact of area-IO on FPLDs from a theoretical and experimental standpoint and show that the introduction of area IO generally improves the routability and delay of a set of benchmark circuits.

关键词： Logic design

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Making visible the thermal behaviour of embedded microprocessors on FPGAs. A progress report

Making visible the thermal behaviour of embedded microproces...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Lopez-Buedo, Sergio Boemo, Eduardo Computer Engineering Department School of Engineering Universidad Autonoma de Madrid Spain

This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working beyond specifications. The idea is to extract the output frequencies of an array of ring-oscillators previously distributed in the die, taking full advantage of the configuration port capabilities in Xilinx technology. As a result, it is shown that the FPGA technology offers the designers of embedded systems the possibility of viewing a detailed thermal map of a circuit at a minimum cost. The verification can be done in actual working conditions;for example with heat sinks and fans attached to the chip, inside the system case, or even in an on-board satellite application. The main results of the work are unthinkable using other alternatives like IR cameras, external sensors, or embedded diodes.

关键词： field programmable gate arrays

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Exploration of pipelined FPGA interconnect structures

Exploration of pipelined FPGA interconnect structures

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Sharma, Akshay Compton, Katherine Ebeling, Carl Hauck, Scott Electrical Engineering University of Washington Seattle WA United States Electrical and Computer Engineering Northwestern University Evanston IL United States Computer Science and Engineering University of Washington Seattle WA United States

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

关键词： field programmable gate arrays

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SMAP: Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

SMAP: Heterogeneous technology mapping for area reduction in...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Wilton, Steven J.E. Univ of British Columbia Vancouver Canada

It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided. This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In order to efficiently use the embedded arrays in this way, a technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array is required. In this paper, we describe such an algorithm. The new tool, called SMAP, packs as much circuit information as possible into the available memory arrays, and maps the rest of the circuit into four-input lookup-tables. On a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 60 4-LUTs into a single 2-Kbit memory array. If there are 16 arrays available, it can map, on average, 358 4-LUTs to the 16 arrays.

关键词： field programmable gate arrays

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I/O placement for FPGAs with multiple I/O standards

I/O placement for FPGAs with multiple I/O standards

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Mak, Wai-Kei Dept. of Comp. Sci. and Eng. University of South Florida Tampa FL 33620 United States

In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer linear programming formulation for the constrained I/O placement problem. The size of the integer linear program derived is independent of the number of I/O objects to be placed and hence is scalable to very large design instances. For example, for a Xilinx Virtex-E FPGA, the number of integer variables required is never more than 32 and is much smaller for practical design instances. Extensive experimental results using a non-commercial integer linear program solver shows that it only takes seconds to solve the resultant integer linear program in practice.

关键词： field programmable gate arrays

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Enabling a realtime solution for neuron detection with reconfigurable hardware

Enabling a realtime solution for neuron detection with recon...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Cordes, Ben Dy, Jennifer Leeser, Miriam Goebel, James Dept. of Electrical and Computer Engineering Northeastern University Boston MA Neural Arts Inc. Decatur GA

FPGAs provide a speed advantage in processing for embedded systems, especially when processing is moved close to the sensors. Perhaps the ultimate embedded system is a neural prosthetic, where probes are inserted into the brain and recorded electrical activity is analyzed to determine which neurons have fired. In turn, this information can be used to manipulate an external device such as a robot arm or a computer mouse. To make the detection of these signals possible, some baseline data must be processed to correlate impulses to particular neurons. One method for processing this data uses a statistical clustering algorithm called Expectation Maximization, or EM. In this paper, we examine the EM clustering algorithm, determine the most computationally intensive portion, map it onto a reconfigurable device, and show several areas of performance gain.

关键词： field programmable gate arrays

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A novel FPGA logic block for improved arithmetic performance 08

A novel FPGA logic block for improved arithmetic performance

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Parandeh-Afshar, Hadi Brisk, Philip Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 compared to adder trees synthesized using ternary adders. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Improvements to technology mapping for LUT-based FPGAs 06

Improvements to technology mapping for LUT-based FPGAs

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Mishchenko, Alan Chatterjee, Satrajit Brayton, Robert Department of EECS University of California Berkeley United States

ISBN: (纸本)1595932925

The paper presents several improvements to state-of-the-art in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD '04]. Improved cut enumeration computes all K-feasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks, A new technique for on-the-fly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7% smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7% and area by 14%, compared to DAOmap. Copyright 2006 acm.

关键词： field programmable gate arrays

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