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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是141-150 订阅

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FPGA Mux Usage and Routability Estimates without Explicit Routing 23

FPGA Mux Usage and Routability Estimates without Explicit Ro...

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31st acm/sigda international symposium on field programmable gate arrays (FPGA)

作者： Greene, Jonathan W. Univ Calif Berkeley Berkeley CA 94720 USA Cambios Comp LLC Berkeley CA 92121 USA

ISBN: (纸本)9781450394178

A new algorithm is proposed to rapidly evaluate an FPGA routing architecture without need of explicitly routing benchmark applications. The algorithm takes as input a probability distribution of nets to be accommodated and a description of an architecture. It produces an estimate for the usage of each type of mux in the FPGA (including intra-cluster muxes), valuable feedback to the architect. The estimates are shown to correlate with actual routed applications in both academic and commercial architectures. This is due in part to the algorithm's novel ability to account for long and multi-fanout nets. Run time is reduced by applying periodic graphs to model FPGAs' regular structure. We then show how Percolation Theory (a branch of statistical physics) can be applied to elucidate the relationship between mux usage and routability. We show that any blockages when routing a net are most likely to occur in the neighborhood of its terminals, and demonstrate a quantitative relationship among the post-placement wirelength of an application, the percolation threshold of an architecture, and the channel width required to map the application to the architecture. Supporting experimental data is provided.

关键词： FPGAs programmable routing percolation theory

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Faithful single-precision floating-point tangent for FPGAs 13

Faithful single-precision floating-point tangent for FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre High Wycombe United Kingdom

ISBN: (纸本)9781450318877

This paper presents an FPGA-specific implementation of the floating-point tangent function. The implementation inputs values in the interval [-π/2,π/2], targets the IEEE-754 single-precision format and has an accuracy of 1 ulp. The proposed work is based on a combination of mathematical identities and properties of the tangent function in floating point. The architecture was designed having the {Stratix-IV} DSP and memory blocks in mind but should map well on any contemporary FPGA featuring embedded multiplier and memory blocks. It outperforms generic polynomial approximation targeting the same resource spectrum and provides better resources trade-offs than classical CORDIC-based *** presented work is widely available as being part of the Altera DSP Builder Advanced Blockset. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Real-time high-definition stereo matching on FPGA 11

Real-time high-definition stereo matching on FPGA

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Zhang, Lu Zhang, Ke Chang, Tian Sheuan Lafruit, Gauthier Kuzmanov, Georgi Krasimirov Verkest, Diederik Delft University of Technology Mekelweq 4 2600GA Delft Netherlands IMEC Kapeldreef 75 B-3001 Leuven Belgium National Chiao Tung University 1001 TaHsueh Rd. Hsinchu Taiwan

ISBN: (纸本)9781450305549

Although many fast stereo matching designs have been proposed in the past decades, it is still very challenging to achieve real-time speed at high definition resolution while maintaining high matching accuracy. In this paper, we propose a real-time high definition stereo matching design on FPGA. By using the Mini-Census transform and the Cross-based cost aggregation, the proposed algorithm is robust to radiometric differences and produces accurate disparity maps. The algorithm modules have been optimized for efficient hardware implementations and instantiated in an SoC environment. Implemented on a single EP3SL150 FPGA, our design achieves 60 frames per second for 1024 × 768 stereo images. Evaluated with the Middlebury stereo benchmark, the proposed design also delivers leading stereo matching accuracy among prior related work. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

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Evolving computer programs using rapidly reconfigurable field-programmable gate arrays and genetic programming 98

Evolving computer programs using rapidly reconfigurable fiel...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Koza, John R. Bennett III, Forrest H. Hutchings, Jeffrey L. Bade, Stephen L. Keane, Martin A. Andre, David Stanford Univ Stanford CA United States

ISBN: (纸本)9780897919784

This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitness measurement task of genetic algorithms and genetic programming. This acceleration is accomplished by embodying each individual of the evolving population into hardware in order to perform the fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O'Connor and Nelson patent on sorting networks (and the same number of steps as a 7-sorter that was devised by Floyd and Knuth subsequent to the patent and that is now known to be minimal). Other minimal sorters have been evolved.

关键词： field programmable gate arrays

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Interactive debugging at ip block interfaces in fpgas 21

Interactive debugging at ip block interfaces in fpgas

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2021 acm/sigda international symposium on field-programmable gate arrays, FPGA 2021

作者： Merlini, Marco Antonio Poy, Isamu Chow, Paul University of Toronto TorontoON Canada

ISBN: (纸本)9781450382182

Recent developments have shown FPGAs to be effective for data centre applications, but debugging support in that environment has not evolved correspondingly. This presents an additional barrier to widespread adoption. This work proposes Debug Governors, a new open-source debugger designed for controllability and interactive debugging that can help to locate issues across multiple FPGAs. A Debug Governor can pause, log, drop, and/or inject data into any streaming interface. These operations enable single-stepping, unit testing, and interfacing with software. Hundreds of Debug Governors can fit in a single FPGA and, because they are transparent when inactive, can be left "dormant"in production designs. We show how Debug Governors can be used to resolve functional problems on a real FPGA, and how they can be extended to memory-mapped protocols. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Verifying the correctness of FPGA logic synthesis algorithms

Verifying the correctness of FPGA logic synthesis algorithms

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Ratchev, Boris Hutton, Mike Baeckler, Gregg Van Antwerpen, Babette Altera Corporation 101 Innovation Drive San Jose CA 95134 United States

Though verification is significantly easier for FPGA-based digital systems than for ASIC or full-custom hardware, there are nonetheless many places for errors to occur. In this paper we discuss the verification problem for FPGAs and describe several methods for verifying end-to-end correctness of synthesis algorithms, a particularly complex portion of the CAD flow. Though the primary contribution of this paper is the analysis of the overall problem, we also give an algorithm for the automatic generation of test-vectors for simulation using information from the synthesis tool, and describe a second testing method that generates purposefully difficult designs in combination with input vectors to test them. We will show the validity of these methods by standard metrics such as simulation node-coverage and through the ability for the method to locate forced errors introduced by the synthesis tool.

关键词： field programmable gate arrays

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Exploration of heterogeneous reconfigurable architectures

Exploration of heterogeneous reconfigurable architectures

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Smith, Alastair M. Constantinides, George A. Cheung, Peter Y. K. Department of Electrical and Electronic Engineering Imperial College London United Kingdom

The purpose of this paper is to detail the method and findings of an architectural exploration of mixed granularity field programmable gate arrays (FPGAs). The work carried out for the purposes of this study involves the creation of an analytical framework within which a set of benchmark circuits can be studied. The idea is to maximise the performance over all benchmark circuits by choosing an optimal set of silicon cores to be placed within a given area constraint. When connected with flexible configurable routing, these cores should together be capable of performing any one of the benchmark circuits. In this paper the problem is cast as a formal optimisation, and solved using existing optimisation tools. Any multiplication or memory operation is allowed to be implemented either by configuring fine-grain resources, or by using specialised functional units such as those found in a Xilinx Virtex 2 FPGA. The design space is explored by examining the tradeoffs between area, speed and flexibility. The architectures generated are contrasted to commercial architectures with fixed ratios of functional units and, in addition, a sensitivity analysis is performed to see how the results are affected by the archtectural parameters of the problem.

关键词： field programmable gate arrays

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Towards Scalable FPGA CAD Through Architecture 11

Towards Scalable FPGA CAD Through Architecture

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19th Annual acm international symposium on field-programmable gate arrays

作者： Chin, Scott Y. L. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical. Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

关键词： field-programmable gate arrays FPGAs Architecture CAD Run-time

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Using bus-based connections to improve field-programmable gate Array density for implementing datapath circuits 05

Using bus-based connections to improve Field-Programmable Ga...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Ye, Andy Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)9781595930293

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This paper describes such an FPGA routing architecture, called the multi-bit routing architecture, which employs bus-based connections in order to exploit datapath regularity. It is experimentally shown that, comparing to conventional FPGA routing architectures, the multi-bit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which represents an overall FPGA area savings of 10%. This paper also empirically determines the best values of several important architectural parameters for the new routing architecture including the most area efficient granularity values and the most area efficient proportion of bus-based connections. Copyright 2005 acm.

关键词： field programmable gate arrays

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GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths 16

GPU-Accelerated High-Level Synthesis for Bitwidth Optimizati...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Kapre, Nachiket Ye, Deheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781450338561

Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc's GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10-1000x speedups for range analysis and 50-200x speedups for bitwidth allocation when comparing NVIDIA K20 GPU implementation to an Intel Core i5-4570 CPU while maintaining identical solution quality across various benchmarks. This allows us to generate tailor-made RTL with minimum bitwidths in hundreds of milliseconds instead of hundreds of minutes when starting from high-level C descriptions of dataflow computations.

关键词： field programmable gate arrays (FPGA)

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