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Reducing pin and area overhead in fault-tolerant FPGA-based designs

Reducing pin and area overhead in fault-tolerant FPGA-based ...

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lima, Fernanda Carro, Luigi Reis, Ricardo Univ. Federal do Rio Grande do Sul PPGC - Inst. de Informatica - DELET Caixa Postal: 15064 CEP 91501-970 - Porto Alegre - RS Brazil

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However. TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

关键词： field programmable gate arrays

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Routing algorithms: Enhancing routability & enabling ECO

Routing algorithms: Enhancing routability & enabling ECO

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Taghavi, Taraneh Ghiasi, Soheil Sarrafzadeh, Majid Computer Science Department University of California 3256N Boelter Hall Los Angeles 90095

The routing channels of today's FPGAs consist of wire segments of various types. This routing architecture makes us capable of exploiting some new techniques to enhance the routability of net segments in channels in order to support engineering change order (ECO). In this paper we present an optimal greedy algorithm to switch the track, which each net segment is assigned to, in order to enhance the routability of newly added nets for enabling ECO. We used the routing architecture of Virtex II FPGAs from Xilinx as our target routing architecture and integrated our algorithm into VPR FPGA routing tool. The experimental result show that the algorithm reduces the number of Tracks by 9% in average. It allows 28.4% more rerouting than the existing router of VPR tool, which is based on Dijkestra's maze router algorithm.

关键词： field programmable gate arrays

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A soft error vulnerability analysis framework for xilinx FPGAs 14

A soft error vulnerability analysis framework for xilinx FPG...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Sari, Aitzan Agiakatsikas, Dimitris Psarakis, Mihalis Department of Informatics University of Piraeus Greece

ISBN: (纸本)9781450326711

Today's SRAM-based FPGAs provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of FPGA designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx FPGA devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

关键词： field programmable gate arrays (FPGA)

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Power estimation approach for SRAM-based FPGAs

Power estimation approach for SRAM-based FPGAs

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Weiss, Karlheinz Oetker, Carsten Katchan, Igor Steckstor, Thorsten Rosenstiel, Wolfgang Forschungszentrum Informatik Karslruhe Germany

This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family. We determined an appropriate technology-dependent power factor Kp to calculate the power consumption on Virtex-chips, and developed a special benchmark test design to conduct our investigations. Additionally, the derived formulas are evaluated on two typical industrial designs. Our own emulation environments called SPYDER-ASIC-X1 and SPYDER-VIRTEX-X2 were used, which are best suited for the emulation of hardware designs for embedded systems.

关键词： field programmable gate arrays

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Using logic duplication to improve performance in FPGAs

Using logic duplication to improve performance in FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Schabas, Karl Brown, Stephen D. Dept. of Elec. and Comp. Eng. University of Toronto Toronto Ont. Canada

The purpose of this paper is to introduce a modified packing and placement algorithm for FPGAs that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic logic elements (BLEs) in timing critical clusters, to allow potential targets for logic duplication. The modified placement algorithm consists of a new stage after placement in which logic duplication is performed to shorten the length of the critical path. In this paper, we show that in a representative FPGA architecture using .18 μm technology, the length of the final critical path can be reduced by an average of 14.1%. Approximately half of this gain comes directly from the changes to the packing algorithm while the other half comes from the logic duplication performed during placement.

关键词： field programmable gate arrays

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FPGA Mux Usage and Routability Estimates without Explicit Routing 23

FPGA Mux Usage and Routability Estimates without Explicit Ro...

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31st acm/sigda international symposium on field programmable gate arrays (FPGA)

作者： Greene, Jonathan W. Univ Calif Berkeley Berkeley CA 94720 USA Cambios Comp LLC Berkeley CA 92121 USA

ISBN: (纸本)9781450394178

A new algorithm is proposed to rapidly evaluate an FPGA routing architecture without need of explicitly routing benchmark applications. The algorithm takes as input a probability distribution of nets to be accommodated and a description of an architecture. It produces an estimate for the usage of each type of mux in the FPGA (including intra-cluster muxes), valuable feedback to the architect. The estimates are shown to correlate with actual routed applications in both academic and commercial architectures. This is due in part to the algorithm's novel ability to account for long and multi-fanout nets. Run time is reduced by applying periodic graphs to model FPGAs' regular structure. We then show how Percolation Theory (a branch of statistical physics) can be applied to elucidate the relationship between mux usage and routability. We show that any blockages when routing a net are most likely to occur in the neighborhood of its terminals, and demonstrate a quantitative relationship among the post-placement wirelength of an application, the percolation threshold of an architecture, and the channel width required to map the application to the architecture. Supporting experimental data is provided.

关键词： FPGAs programmable routing percolation theory

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Data reorganization engines for the next generation of system-on-a-chip FPGAs 02

Data reorganization engines for the next generation of syste...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Diniz, Pedro C. Park, Joonseok University of Southern California Information Sciences Institute 4676 Admiralty Way Marina del Rey CA 90292 United States

ISBN: (纸本)9781581134520

field-programmable-Core-arrays (FPCA) will include various computing cores for a wide variety of applications ranging from DSP to general purpose computing. With the increasing gap between core computing speeds and memory access latency, managing and orchestrating the movement of data across multiple cores will become increasingly important. In this paper we propose data reorganization engines that allow a wide variety of data reorganizations intra- as well as inter-memory modules for future FPCAs. We have experimented with a suite of data reorganizations pervasive in DSP applications. Our limited set of experiments reveals that the proposed designs for these engines are flexile and use little design area in current FPGA fabrics, making them amenable to be easily integrated in future FPCAs as either soft- or hard- macros.

关键词： field programmable gate arrays

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Interconnect enhancements for a high-speed PLD architecture 02

Interconnect enhancements for a high-speed PLD architecture

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Hutton, Michael Chan, Vinson Kazarian, Peter Maruri, Victor Ngai, Tony Park, Jim Patel, Rakesh Pedersen, Bruce Schleicher, Jay Shumarayev, Sergey Altera Corporation 101 Innovation Drive San Jose CA 95134 United States

ISBN: (纸本)9781581134520

As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.

关键词： field programmable gate arrays

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Timing driven floorplanning on programmable hierarchical targets 98

Timing driven floorplanning on programmable hierarchical tar...

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Senouci, S.A. Amoura, A. Krupnova, H. Saucier, G. Inst Natl Polytechnique de Grenoble/CSI Grenoble France

ISBN: (纸本)9780897919784

The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following its hierarchy. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided by this cone structuring and has two innovative features: first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, thus a significant reduction is obtained;second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.

关键词： Timing circuits

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Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability 05

Power modeling and architecture evaluation for FPGA with nov...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Lin, Yan Li, Fei He, Lei Electrical Engineering Department University of California Los Angeles United States

ISBN: (纸本)9781595930293

Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be power-gated. In this paper, we first develop an accurate FPGA power model and then design novel Vdd-programmable interconnect switches with minimum number of configuration SRAM cells. Applying our power model to placed and routed benchmark circuits, we evaluate Vddprogrammable FPGA architecture using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, the best architecture reduces the minimal energy-delay product by 44.14% with 48% area overhead and 3% SRAM cell increase. Our evaluation results also show that LUT size 4 always gives the lowest energy consumption while LUT size 7 always leads to the highest performance for all evaluated architectures. Copyright 2005 acm.

关键词： field programmable gate arrays

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