检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

599 篇 会议
30 篇 期刊文献

馆藏范围

629 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

511 篇 工学
- 469 篇 计算机科学与技术...
- 285 篇 软件工程
- 225 篇 电子科学与技术（可...
- 144 篇 电气工程
- 88 篇 信息与通信工程
- 35 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 26 篇 机械工程
- 15 篇 生物工程
- 13 篇 仪器科学与技术
- 9 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 材料科学与工程（可...
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 3 篇 农业工程
203 篇 理学
- 170 篇 数学
- 35 篇 物理学
- 19 篇 统计学（可授理学、...
- 16 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
54 篇 管理学
- 46 篇 管理科学与工程(可...
- 29 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学

主题

275 篇 field programmab...
172 篇 field programmab...
35 篇 signal processin...
35 篇 clocks
33 篇 modulation
33 篇 ofdm
33 篇 estimation
33 篇 filtration
30 篇 fpga
9 篇 table lookup
9 篇 routing
9 篇 systolic arrays
9 篇 switches
8 篇 field-programmab...
7 篇 fpgas
7 篇 optimization
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university
3 篇 state key lab of...
3 篇 computer science...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

622 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A remote memory access infrastructure for global address space programming models in FPGAs 13

A remote memory access infrastructure for global address spa...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Willenberg, Ruediger Chow, Paul Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450318877

We are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for FPGA and CPU components in a heterogeneous system. Our intent is to ease the integration of reconfigurable hardware into parallel programming models like Partitioned Global Address Space (PGAS). For this purpose, we introduce a remote memory access component based on Active Messages that implements the core API of the Berkeley GASNet communication library, and a simple controller that manages communication and synchronization for custom FPGA cores. We demonstrate how these components deliver a simple and easily configurable communication mechanism between distributed memories in a multi-FPGA system with processors as well as custom hardware nodes. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Towards simulator-like observability for FPGAs: A virtual overlay network for trace-buffers 13

Towards simulator-like observability for FPGAs: A virtual ov...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Hung, Eddie Wilton, Steven J.E. Dept. of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450318877

The rising complexity of verification has led to an increase in the use of FPGA prototyping, which can run at significantly higher operating frequencies and achieve much higher coverage than logic simulations. However, a key challenge is observability into these devices, which can be solved by embedding trace-buffers to record on-chip signal values. Rather than connecting a predetermined subset of circuits signals to dedicated trace-buffer inputs at compile-time, in this work we propose that a virtual overlay network is built to multiplex all on-chip signals to all on-chip trace-buffers. Subsequently, at debug-time, the designer can choose a signal subset for observation. To minimize its overhead, we build this network out of unused routing multiplexers, and by using optimal bipartite graph matching techniques, we show that any subset of on-chip signals can be connected to 80-90% of the maximum trace-buffer capacity in less than 50 seconds. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Architectural enhancements in Stratix V™ 13

Architectural enhancements in Stratix V™

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Lewis, David Cashman, David Chan, Mark Chromczak, Jeffery Lai, Gary Lee, Andy Vanderhoek, Tim Yu, Haiming Altera Corporation 101 Innovation Drive San Jose CA 95134 United States Altera Corporation 150 Bloor St W. Toronto ON M5S 2X9 Canada

ISBN: (纸本)9781450318877

This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

High-level synthesis with LegUp: A crash course for users and researchers 13

High-level synthesis with LegUp: A crash course for users an...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Anderson, Jason H. Brown, Stephen D. Canis, Andrew Choi, Jongsok Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450318877

High-level synthesis (HLS) has been gaining traction recently as a design methodology for FPGAs, with the promise of raising the productivity of FPGA hardware designers, and ultimately, opening the door to the use of FPGAs as computing devices targetable by software engineers. In this tutorial, we introduce LegUp, an open-source HLS tool for FPGAs developed at the University of Toronto. With LegUp, a user can compile a C program completely to hardware, or alternately, he/she can choose to compile the program to a hybrid hardware/software system comprising a processor along with one or more accelerators. LegUp supports the synthesis of most of the C language to hardware, including loops, structs, multi-dimensional arrays, pointer arithmetic, and floating point operations. The LegUp distribution includes the CHStone HLS benchmark suite, as well as a test suite and associated infrastructure for measuring quality of results, and for verifying the functionality of LegUp-generated circuits. LegUp is freely downloadable at ***, providing a powerful platform that can be leveraged for new high-level synthesis research. © 2013 Authors.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Sensing nanosecond-scale voltage attacks and natural transients in FPGAs 13

Sensing nanosecond-scale voltage attacks and natural transie...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Zick, Kenneth M. Srivastav, Meeta Zhang, Wei French, Matthew Arlington VA United States Virginia Tech. Blacksburg VA United States University of Virginia Charlottesville VA United States

ISBN: (纸本)9781450318877

Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to FPGA-based systems and presents a solution approach. Novel measurements of transients on 28nm FPGAs show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented;its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Accelerating ncRNA homology search with FPGAs 13

Accelerating ncRNA homology search with FPGAs

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： McVicar, Nathaniel Ruzzo, Walter L. Hauck, Scott Department of Electrical Engineering University of Washington Seattle WA 98195 United States Department of Computer Science and Engineering Department of Genome Sciences Fred Hutchinson Cancer Research Center Seattle WA 98109 United States

ISBN: (纸本)9781450318877

Over the last decade, the number of known biologically important non-coding RNAs (ncRNAs) has increased by orders of magnitude. The function performed by a specific ncRNA is partially determined by its structure, defined by which nucleotides of the molecule form pairs. These correlations may span large and variable distances in the linear RNA molecule. Because of these characteristics, algorithms that search for ncRNAs belonging to known families are computationally expensive, often taking many CPU weeks to run. To improve the speed of this search, multiple search algorithms arranged into a series of progressively more stringent filters can be used. In this paper, we present an FPGA based implementation of some of these algorithms. This is the first FPGA based approach to attempt to accelerate multiple filters used in ncRNA search. The FPGA is reconfigured for each filter, resulting in a total system speedup of 25x when compared with a single CPU. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Power estimation tool for system on programmable chip based platforms (abstract only) 14

Power estimation tool for system on programmable chip based ...

引用

proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Santhosh Kumar Rethinagiri Oscar Palomar Adrian Cristal Osman Unsal BSC - Microsoft Research Center Barcelona Spain BSC - Mircrosoft Research Center Barcelona Spain

ISBN: (纸本)9781450326711

The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core *** effectiveness of our proposed tool is validated through dualcore RISC processor designed around the FPGA board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other

关键词： power/energy estimation fpga systemc heterogeneous architecture asic tlm speedup multicore functional power models design space exploration virtual platform accuracy

来源：评论

学校读者我要写书评

暂无评论

Heracles: A tool for fast RTL-based design space exploration of multicore processors 13

Heracles: A tool for fast RTL-based design space exploration...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Kinsy, Michel A. Pellauer, Michael Devadas, Srinivas Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA United States Intel Corporation VSSAD Group Hudson MA United States

ISBN: (纸本)9781450318877

This paper presents Heracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of different topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly configure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are FPGA platform independent. The Heracles tool is freely available under the open-source MIT license at: http://***/heracles. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Placement of repair circuits for in-field FPGA repair 13

Placement of repair circuits for in-field FPGA repair

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Wirthlin, Michael Jensen, Josh Wilson, Alex Howes, Will Wen, Shi-Jie Wong, Rick Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84606 United States Cisco Systems San Jose CA 95134 United States

ISBN: (纸本)9781450318877

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This paper presents a method for repairing FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found in any logic block of the FPGA. This approach relies on logic placement to create "repair" circuits that avoid specific logic blocks. Three repair placement algorithms will be presented that generate a complete set of repair designs during the conventional placement process. The number of repairs needed to create a complete repair set depends heavily on the utilization of the FPGA resources. The three algorithms are tested against several benchmarks and with multiple area constraints for each benchmark. The best repair placement approach described in the paper generates a full set of repair circuits at a computation cost of 16X that of a conventional placer and with circuits of comparable quality. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Area-efficient near-associative memories on FPGAs 13

Area-efficient near-associative memories on FPGAs

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Dhawan, Udit DeHon, André Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Associative memories can map sparsely used keys to values with low latency but can incur heavy area overheads. The lack of customized hardware for associative memories in today's mainstream FPGAs exacerbates the overhead cost of building these memories using the fixed address match BRAMs. In this paper, we develop a new, FPGA-friendly, memory architecture based on a multiple hash scheme that is able to achieve near-associative performance (less than 5% of evictions due to conflicts) without the area overheads of a fully associative memory on FPGAs. Using the proposed architecture as a 64KB L1 data cache, we show that it is able to achieve near-associative miss-rates while consuming 6-7× less FPGA memory resources for a set of benchmark programs from the SPEC2006 suite than fully associative memories generated by the Xilinx Coregen tool. Benefits increase with match width, allowing area reduction up to 100×. At the same time, the new architecture has lower latency than the fully associative memory - 3.7 ns for a 1024-entry flat version or 6.1 ns for an area-efficient version compared to 8.8 ns for a fully associative memory for a 64b key. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共63页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：