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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2011年 iii页

作者： Wawrzynek, John Compton, Katherine UC Berkeley United States University of Wisconsin-Madison United States

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Improving high level synthesis optimization opportunity through polyhedral transformations 13

Improving high level synthesis optimization opportunity thro...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Zuo, Wei Liang, Yun Li, Peng Rupnow, Kyle Chen, Deming Cong, Jason Center for Energy-Efficient Computing and Applications School of EECS Peking University China University of Illinois Urbana-Champaign IL United States Advanced Digital Science Center Singapore Singapore Computer Science Department University of California Los Angeles CA United States School of Information and Electronics Beijing Institute of Technology China

ISBN: (纸本)9781450318877

High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art high level synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. These optimizations can implement some of the most important features generally performed in manual designs including parallel hardware units, pipelining of execution both within a hardware unit and between units, and fine-grained data communication. We may generally classify the optimizations as those that optimize hardware implementation within a code block (intra-block) and those that optimize communication and pipelining between code blocks (inter-block). However, both optimizations are in practice difficult to apply. Real-world applications contain data-dependent blocks of code and communicate through complex data access patterns. Existing high level synthesis tools cannot apply these powerful optimizations unless the code is inherently compatible, severely limiting the optimization opportunity. In this paper we present an integrated framework to model and enable both intra- and inter-block optimizations. This integrated technique substantially improves the opportunity to use the powerful HLS optimizations that implement parallelism, pipelining, and fine-grained communication. Our polyhedral model-based technique systematically defines a set of data access patterns, identifies effective data access patterns, and performs the loop transformations to enable the intra- and inter-block optimizations. Our framework automatically explores transformation options, performs code transformations, and inserts the appropriate HLS directives to implement the HLS optimizations. Furthermore, our framework can automatically generate the optimized communication blocks for fine-grained communica

关键词： field programmable gate arrays (FPGA)

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Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources 13

Pipeline template and scheduling algorithm for mapping multi...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Dong, Yazhuo Zhan, Wu Ye, Xiqing Naval Academy of Armament No. 3 Wanshou Street Haidian area Beijing City 100036 China

ISBN: (纸本)9781450319027

There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. FPGA provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a parameterized pipeline template to execute all the loop nests in sequence without FPGA reconfiguration. Five steps are designed to decide the parameters. Experiments show that the pipeline template can achieve a comparative execution cycles for a loop comparing with the special hardware structure. © 2013 Authors.

关键词： field programmable gate arrays (FPGA)

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Heterogeneous 3-D stacking, can we have the best of both (Technology) worlds? 13

Heterogeneous 3-D stacking, can we have the best of both (Te...

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2013 acm international symposium on Physical Design, ISPD 2013

作者： Madden, Liam Xilinx Inc. 2100 Logic Drive San Jose CA 95124 United States

ISBN: (纸本)9781450318679

Since the advent of integrated circuit technology in 1958, the industry has focused primarily on monolithic integration. Unfortunately, due to physical and economic issues, the vast majority of high performance analog chips, high density memory chips, and high performance digital chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). The heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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A compact FPGA-based Montgomery multiplier over prime fields 13

A compact FPGA-based Montgomery multiplier over prime fields

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Morales-Sandoval, Miguel Díaz-Pérez, Arturo Laboratorio de Tecnologías de la Información CINVESTAV-Tamaulipas Ciudad Victoria 87130 Mexico

ISBN: (纸本)9781450319027

This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(p) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form β = 2k. The design uses only three k x k multipliers and three 2k-bit adders. The hardware organization of the multiplier maximizes the use of the multipliers processing iteratively the multiplicand, multiplier and modulus. The parametric design allows to study area-performance trade offs, in order to meet system requirements such as available resources, throughput, and efficiency. The proposed multiplier achieves a 1024-bit modular multiplication in 15.63 μs using k = 32. Compared to the most compact FPGA implementation previously reported, our proposed design uses 79% less FPGA resources with better efficiency expressed as Mbps/Slice. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware 13

A hardware-oriented dynamically adaptive disparity estimatio...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Akin, Abdulkadir Baz, Ipek Atakan, Baris Boybat, Irem Schmid, Alexandre Leblebici, Yusuf STI EPFL 1015 Lausanne Switzerland EEE METU Ankara Turkey EE SU Istanbul Turkey

ISBN: (纸本)9781450319027

The computational complexity of disparity estimation algorithms and the need of large size and bandwidth for the external and internal memory make the real-time processing of disparity estimation challenging, especially for High Resolution (HR) images. This paper proposes a hardware-oriented adaptive window size disparity estimation (AWDE) algorithm and its real-time reconfigurable hardware implementation that targets HR video with high quality disparity results. The proposed algorithm is a hybrid solution involving the Sum of Absolute Differences and the Census cost computation methods to vote and select the best suitable disparity candidates. It utilizes a pixel intensity based refinement step to remove faulty disparity computations. The AWDE algorithm dynamically adapts the window size considering the local texture of the image to increase the disparity estimation quality. The proposed reconfigurable hardware of the AWDE algorithm enables handling 60 frames per second on Virtex-5 FPGA at a 1024x768 XGA video resolution for a 120 pixel disparity range. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only) 13

Hardware acceleration of TEA and XTEA algorithms on FPGA, GP...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vivek Venugopal Devu Manikantan Shila United Technologies Research Center E Hartford CT USA

ISBN: (纸本)9781450318877

field programmable gate arrays (FPGA) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with FPGAs for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; FPGAs, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and FPGAs as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and FPGAs. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined FPGA implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

关键词： cryptography graphics processing units tiny encryption algorithm field programmable gate arrays parallel processing

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Indirect connection aware attraction for FPGA clustering (abstract only) 13

Indirect connection aware attraction for FPGA clustering (ab...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Meng Yang Jiarong Tong A.E.A. Almaini State Key Lab of ASIC Fudan University Shanghai China Edinburgh Napier University Edinburgh United Kingdom

ISBN: (纸本)9781450318877

Indirect connection aware attraction clustering algorithm is proposed for clustered field programmable gate array architecture model to achieve simultaneously optimization of several performance metrics. A new cost function considers the attraction of the subsequent basic logic elements (BLEs) to the selected cluster, the number of the used pins already in the cluster, as well as critical path delay. The attractions of which BLEs are directly and indirectly connected to the selected cluster are taken into account. As a result, more external nets are absorbed into clusters, less number of pins per cluster and fewer clusters are required. Hence, smaller channel width is required for routing and speed of the design is improved. Performance comparisons are carried out in details with respect to state-of-the-art clustering techniques interconnect resource aware clustering (iRAC) and many-objective clustering (MO-Pack). Results show that the proposed algorithm outperforms these two clustering approaches with achievements of 38.8% and 42.2% respectively in terms of channel widths and 40.1% and 44.8% respectively in terms of number of external nets but with no critical path and area overhead.

关键词： FPGAs computer aided design clustering optimization field-programmable gate arrays

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FPGA-based HPC application design for non-experts (abstract only) 13

FPGA-based HPC application design for non-experts (abstract ...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

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Are FPGAs suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

FPGAs constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the FPGA community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current FPGA market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for FPGA-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the FPGA industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

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