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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是251-260 订阅

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Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only) 13

Hybrid masking using intra-masking dual-rail memory on LUT f...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Anh-Tuan Hoang Takeshi Fujino Ritsumeikan University Shiga prefecture Kusatsu city Japan

ISBN: (纸本)9781450318877

In current countermeasure design trends against Different Power Analysis (DPA), security at gate level is required in addition to the security algorithm. Several Dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate Array (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel Hybrid Masking implementations using Intra-Masking Dual-rail Memory (IMDRM) approach for Side-channel-resistant AES. The hybrid masking scheme includes an additive mask and a multiplicative mask. The additive masking scheme utilizes a dual-rail memory, in which all unsafe nodes, such as unmasking and masking, the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The multiplicative masking scheme is then applied over the additive masked values. It removes the joint-leakage, which is caused by the joint processing of the masks and the masked values inside the dual-rail memory. The design is independent of the cryptographic algorithm and persistent with SCA attacks even after 1,000,000 traces. It also occupied smaller hardware size than most other advanced SCA resistant implementations such as the Wave Dynamic Differential Logic, the Masked Dual-Rail Pre-charge Logic, and the Intra-Masking Dual-Rail Memory.

关键词： SCA resistance differential power analysis (DPA) side-channel attack masking intra-masking dual-rail memory on LUT dual-rail memory field programmable gate array (FPGA) hybrid masking AES

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Defect recovery in nanodevice-based programmable interconnects (abstract only) 13

Defect recovery in nanodevice-based programmable interconnec...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Bingjun Xiao UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

This work focuses on defect tolerance for nanodevice-based programmable interconnects of FPGAs. A single nanodevice can function as a routing switch in place of a pass transistor and its six-transistor SRAM cell in conventional FPGAs. Defects of nanodevices in programmable interconnects are manifested as losses of configurability and can be categorized into stuck- open defect and stuck- closed defect. First, we show that the stuck-closed defects of nanodevices have a much higher impact than the stuck-open defects. Instead of simply avoiding the stuck-closed defects, we recover them by treating them as shorting constraints in the routing. We develop a scalable algorithm to perform timing-driven routing under these extra constraints. We extend the idea of the resource negotiation to balance the goals of timing and routability under shorting constraints. We also develop several techniques to guide the router to map the shorting clusters to those nets with more shared paths for better utilization of routing resources while automatically balancing it with circuit performance. We also enhance the placement algorithm to recover logic blocks which become virtually unusable due to shorted pins. Simulation results show that at the up-to-date level of nanodevice defects (108-1011x higher than CMOS), compared to the simple avoidance method, our approach reduces the degradation of resource usage by 87%, improves the routability by 37%, and reduce the degradation of circuit performance by 36%, at a negligible overhead of tool runtime.

关键词： nanodevice defect tolerance route programmable interconnects placement

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A Fast Discrete Placement Algorithm for FPGAs 12

A Fast Discrete Placement Algorithm for FPGAs

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good FPGA placement is crucial to obtain the best Quality of Results (QoR) from FPGA hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, FPGAs are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete FPGA-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (FPGA) placement simulated annealing

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Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (FPGA) Floating-point Mantissa Alignment Normalization

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Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on FPGA 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on FPGA for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (FPGA)

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Leveraging latency-insensitivity to ease multiple FPGA design 12

Leveraging latency-insensitivity to ease multiple FPGA desig...

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2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

作者： Fleming, Kermin Elliott Adler, Michael Pellauer, Michael Parashar, Angshuman Mithal, Arvind Emer, Joel Intel Corporation VSSAD Group Hudson MA United States Massachusetts Institute of Technology Computer Science and A.I. Laboratory Cambridge MA United States

ISBN: (纸本)9781450311557

Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance. © 2012 acm.

关键词： field programmable gate arrays (FPGA)

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Impact of FPGA architecture on resource sharing in high-level synthesis 12

Impact of FPGA architecture on resource sharing in high-leve...

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2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

作者： Hadjis, Stefan Canis, Andrew Anderson, Jason H. Choi, Jongsok Nam, Kevin Brown, Stephen Czajkowski, Tomasz ECE Department University of Toronto Toronto ON Canada Altera Toronto Technology Centre Toronto ON Canada

ISBN: (纸本)9781450311557

Resource sharing is a key area-reduction approach in high-level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial FPGA families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs). © 2012 acm.

关键词： field programmable gate arrays (FPGA)

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FPGA'10 - proceedings of the 18th acm sigda international symposium on field-programmable gate arrays

FPGA'10 - Proceedings of the 18th ACM SIGDA International Sy...

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18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

ISBN: (纸本)9781605589114

The proceedings contain 34 papers. The topics discussed include: FPGA prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on FPGAs;energy efficient sensor node implementations;high throughput and large capacity pipelined dynamic search tree on FPGA;FPMR: MapReduce framework on FPGA: a case study of RankBoost acceleration;Axel: a heterogeneous cluster with FPGAs and GPUs;building a faster Boolean matcher using bloom filter;scalable network virtualization using FPGAs;maximizing area-constrained partial fault tolerance in reconfigurable logic;FPGA based chip emulation system for test development and verification of analog and mixed signal circuits;a semi-automatic Toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning;and a dependency graph based methodology for parallelizing HLL applications on FPGA.

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A Complete Power Estimation Methodology for DSP Blocks in FPGAs

A Complete Power Estimation Methodology for DSP Blocks in FP...

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13th international symposium on Quality Electronic Design (ISQED)

作者： Hassan, Hassan Abdallah, Nizar Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781467310369;9781467310352

This work proposes a complete commercial power model for DSP blocks in FPGAs. A pin activities model is developed to estimate the transitions densities at the output of the DSP blocks given the switching activities at the inputs. Such a pin activities model is important in estimating power dissipation during the pre-layout design phase. The power model estimates the total power dissipation in the DSP blocks using the knowledge of all the transitions densities of the inputs and outputs, which are estimated by the proposed pin activities model. The average error of the proposed power model on the design level is less than 2%.

关键词： powered models Digital signal processing Desmoplakin Gene power estimation Power dissipation PIN Bone Nails field programmable gate arrays

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2010年 iii页

作者： Cheung, Peter Wawrzynek, John Imperial College London United Kingdom University of California Berkeley CA United States

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