检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

599 篇 会议
30 篇 期刊文献

馆藏范围

629 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

511 篇 工学
- 469 篇 计算机科学与技术...
- 285 篇 软件工程
- 225 篇 电子科学与技术（可...
- 144 篇 电气工程
- 88 篇 信息与通信工程
- 35 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 26 篇 机械工程
- 15 篇 生物工程
- 13 篇 仪器科学与技术
- 9 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 材料科学与工程（可...
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 3 篇 农业工程
203 篇 理学
- 170 篇 数学
- 35 篇 物理学
- 19 篇 统计学（可授理学、...
- 16 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
54 篇 管理学
- 46 篇 管理科学与工程(可...
- 29 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学

主题

275 篇 field programmab...
172 篇 field programmab...
35 篇 signal processin...
35 篇 clocks
33 篇 modulation
33 篇 ofdm
33 篇 estimation
33 篇 filtration
30 篇 fpga
9 篇 table lookup
9 篇 routing
9 篇 systolic arrays
9 篇 switches
8 篇 field-programmab...
7 篇 fpgas
7 篇 optimization
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university
3 篇 state key lab of...
3 篇 computer science...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

622 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是261-270 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Register leakage masking using Gray code

引用

2012 IEEE international symposium on Hardware-Oriented Security and Trust, HOST 2012

作者： Maghrebi, Houssem Guilley, Sylvain Prouff, Emmanuel Danger, Jean-Luc 37/39 rue Dareau 75 634 Paris Cedex 13 France 51 boulevard de La Tour-Maubourg 75 700 Paris France

ISBN: (纸本)9781467323390

Since their introduction in 1996, the effectiveness of side channel attacks has been highly improved and many countermeasures have been invalidated. A very common countermeasure consists in randomizing sensitive variables of algorithms by masking techniques. In this paper, we propose a new way to apply this strategy to secure hardware implementations of block ciphers. The main advantage of the proposed solution is that the masked variables and the masking material can be manipulated simultaneously without leaking sensitive information in the Hamming distance model. Moreover, we show that the leaking information stays very limited when the deterministic part of the real leakage slightly deviates from the Hamming distance. Finally, we apply our method to protect an AES hardware implementation and we show that the performances are suitable for practical implementations. © 2012 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Power-aware FPGA technology mapping for programmable-VT architectures (abstract only) 12

Power-aware FPGA technology mapping for programmable-VT arch...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wei Ting Loke Yajun Ha Xilinx Asia Pacific Pte. Ltd. & National University of Singapore Singapore Singapore National University of Singapore Singapore Singapore

ISBN: (纸本)9781450311557

In this paper, we present a framework for leakage power reduction in FPGAs with programmable-VT architectures, with focus on dual-VT technology mapping. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the possible strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to tune LUT VT via RBB offer the potential of reducing leakage power with no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs oer some levels of VT programmability, but with optimizations limited to the post-P&R stage. We present a novel technology mapper (RBBMap), logic block packer (RBBPack) and placement-and-routing tool (RBBVPR) that together demonstrate the advantages in moving RBB optimizations upwards to the technology mapping level. Compared to an existing power-optimized technology mapping tool Emap, our framework oers an average of 44.41% savings in average logic block leakage power and 30.88% savings in average total energy consumption. We also illustrate why our work is potentially superior to another comparable work DVMap-2 that utilizes a dual-VDD approach.

关键词： fpga multiple voltage programmable-vt dual-vt reverse back bias technology mapping

来源：评论

学校读者我要写书评

暂无评论

A field programmable array core for image processing (abstract only) 12

A field programmable array core for image processing (abstra...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Declan Walsh Piotr Dudek The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450311557

Massively parallel processor arrays have been shown to be an effective and suitable choice for image processing tasks [1]. More recently, some of the state of the art processor arrays have been used for real-time machine vision tasks such as intelligent transport system applications [2] or video processing on mobile applications [3] providing a much more powerful solution than a conventional processor. A number of Single Instruction Multiple Data (SIMD) processor arrays have been implemented on FPGAs [4]-[6], which are particularly suited to implementing such processor architectures because of their similarities of both being arrays of fine grained logic elements. In this work, we propose an FPGA implementation of a processor array where the processing elements (PEs) are as small as possible, while providing local memory sufficient for processing greyscale images. The PE is then replicated to form an array. A 32 × 32 PE array is implemented on a Xilinx Virtex 5 XC5VLX50 FPGA using the four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 96 MHz and executes a peak of 98.3 giga operations per second (GOPS) (bit-serial operations). A binary edge detection algorithm is performed in 52.08 ns. Uploading and downloading a binary image in a 32 × 32 array takes an extra 687.5 ns. Sobel edge detection of an 8-bit greyscale image is performed in 5.33 µs. Uploading and downloading an 8-bit greyscale image in a 32 × 32 array takes 5.36 µs. With larger FPGAs being available in the future, the array sizes comparable to state of the art custom designed ICs can be implemented on these FPGAs.

关键词： architecture fpga simd image processor array

来源：评论

学校读者我要写书评

暂无评论

Thermal and Power Characterization of field-programmable gate arrays 11

Thermal and Power Characterization of Field-Programmable Gat...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Nowroz, Abdullah Nazma Reda, Sherief Brown Univ Sch Engn Providence RI 02912 USA

ISBN: (纸本)9781450305549

In this paper we propose new techniques for thermal and power characterization of field programmable gate arrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an FPGA chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in FPGAs. Given that FPGAs are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from FPGAs into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.

关键词： Thermal characterization sensors power mapping

来源：评论

学校读者我要写书评

暂无评论

Eliminating the Memory Bottleneck: An FPGA-based Solution for 3D Reverse Time Migration 11

Eliminating the Memory Bottleneck: An FPGA-based Solution fo...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Fu, Haohuan Clapp, Robert G. Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China

ISBN: (纸本)9781450305549

Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with the number of cores in many cases. In our work, we present our FPGA-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RIM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from both the algorithmic and architectural perspectives, our FPGA-based solution manages to remove the memory constraints and provide a high performance that can scale well with the amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 FPGAs, and 8x speedup on two Virtex-6 FPGAs. Our projection demonstrates that the performance will continue to scale with the future increase of FPGA capacities.

关键词： field programmable gate arrays (FPGA) Reverse Time Migration (RTM)

来源：评论

学校读者我要写书评

暂无评论

Scalable and deterministic timing-driven parallel placement for FPGAs 11

Scalable and deterministic timing-driven parallel placement ...

引用

proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Wang, Chris C. Lemieux, Guy G.F. Dept. of ECE University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

This paper describes a parallel implementation of the timing-driven VPR∼5.0 simulated annealing engine. By restricting the move distance to a confined neighborhood, it is possible to consider a large number of non-conflicting moves in parallel and achieve a deterministic result. The full timing-driven algorithm is parallelized, including the detailed timing analysis updates done periodically while placement progresses. The limited move slightly degrades the placement quality, but this is necessary to expose greater degrees of parallelism. The overall bounding box metric degrades about 11% and critical path delay metric degrades about 8% compared to VPR's original algorithm, but we show the amount of degradation is independent of the number of threads. Overall, the parallel implementation scales to a speedup of 123× using 25 threads compared to VPR. With additional tuning effort, we believe the algorithm can be scaled to a larger number of threads, perhaps even run on a GPU, with little additional quality degradation. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Towards Scalable FPGA CAD Through Architecture 11

Towards Scalable FPGA CAD Through Architecture

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Chin, Scott Y. L. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical. Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

关键词： field-programmable gate arrays FPGAs Architecture CAD Run-time

来源：评论

学校读者我要写书评

暂无评论

Real-time high-definition stereo matching on FPGA 11

Real-time high-definition stereo matching on FPGA

引用

proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Zhang, Lu Zhang, Ke Chang, Tian Sheuan Lafruit, Gauthier Kuzmanov, Georgi Krasimirov Verkest, Diederik Delft University of Technology Mekelweq 4 2600GA Delft Netherlands IMEC Kapeldreef 75 B-3001 Leuven Belgium National Chiao Tung University 1001 TaHsueh Rd. Hsinchu Taiwan

ISBN: (纸本)9781450305549

Although many fast stereo matching designs have been proposed in the past decades, it is still very challenging to achieve real-time speed at high definition resolution while maintaining high matching accuracy. In this paper, we propose a real-time high definition stereo matching design on FPGA. By using the Mini-Census transform and the Cross-based cost aggregation, the proposed algorithm is robust to radiometric differences and produces accurate disparity maps. The algorithm modules have been optimized for efficient hardware implementations and instantiated in an SoC environment. Implemented on a single EP3SL150 FPGA, our design achieves 60 frames per second for 1024 × 768 stereo images. Evaluated with the Middlebury stereo benchmark, the proposed design also delivers leading stereo matching accuracy among prior related work. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Power 11

A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Po...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Greene, Jonathan Kaptanoglu, Sinan Feng, Wenyi Hecht, Volker Landry, Joel Li, Fei Krouglyanskiy, Anton Morosan, Mihai Pevzner, Val Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781450305549

This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the IT flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.

关键词： FPGA architecture flash memory Clos network built-in self-test programmable routing input interconnection block IIB packing

来源：评论

学校读者我要写书评

暂无评论

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect 11

Architecture description and packing for logic blocks with h...

引用

proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Luu, Jason Anderson, Jason Helge Rose, Jonathan Scott Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450305549

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共63页 << < 23 24 25 26 27 28 29 30 31 32 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：