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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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proceedings of the 7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

Proceedings of the 7th ACM SIGDA International Symposium on ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

ISBN: (纸本)9781605584102

The proceedings contain 34 papers. The topics discussed include: emerging application domains - research challenges and opportunities for FPGAs;towards automated ECOs in FPGAs;clock power reduction for Virtex-5 FPGAs;choose-your-own-adventure routing: lightweight load-time defect avoidance;towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs;a comparison of via-programmable gate array logic cell circuits;a comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation;a high-performance FPGA architecture for restricted Boltzmann machines;FPGA-based front-end electronics for positron emission tomography;FPGA-based face detection system using Haar classifiers;a 17ps time-to-digital converter implemented in 65nm FPGA technology;and FPGA technology mapping with encoded libraries and staged priority cuts.

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mrFPGA: A novel FPGA architecture with memristor-based reconfiguration 11

mrFPGA: A novel FPGA architecture with memristor-based recon...

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proceedings of the 2011 IEEE/acm international symposium on Nanoscale Architectures

作者： Cong, Jason Xiao, Bingjun Department of Computer Science University of California Los Angeles CA United States

ISBN: (纸本)9781457709944

In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D die-stacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only) 11

Memory based computing: reshaping the fine-grained logic in ...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Somnath Paul Swarup Bhunia Case Western Reserve University Cleveland OH USA

ISBN: (纸本)9781450305549

Conventional field programmable gate Array (FPGA) architectures leverage on the purely spatial computing model where a design is realized in the form of a small multiple-input single-output lookup tables (LUTs) connected through programmable interconnect switches. However, such a model incorporates an elaborate programmable interconnect network which becomes a major performance bottleneck and leads to poor scalability across process technology nodes. In this paper we evaluate an alternative two-dimensional static random access memory (SRAM) array based reconfigurable computing fabric, referred to as "Memory Based Computing" (MBC) that departs from a purely spatial architecture by advocating multi-cycle evaluation at each computational element. Within a computational element, it uses a dense two-dimensional SRAM array to map large multi-input multi-output functions as LUT and evaluate them in time-multiplexed topological fashion. Multi-cycle execution at each computing node is accomplished using a local interconnect architecture. The proposed framework substantially reduces the requirement for global interconnects by folding computational resources onto a single computational element. We explore the design space for MBC to optimize the major design parameters and compare the performance, power dissipation and energy-delay product for benchmark applications between MBC and conventional SRAM-based FPGA. Simulation results show that compared to a clustered FPGA model, the proposed framework achieves 57% improvement in performance, 30% improvement in Energy Delay Product (EDP) and 10% improvement in technological scalability of performance for standard benchmark circuits. Finally, we validate the functionality of MBC framework and timing of different operations by mapping several small applications on a Cyclone III FPGA platform from Altera.

关键词： memory based computation field programmable gate array (fpga) recongurable hardware

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The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop 11

The role of FPGAs in a converged future with heterogeneous p...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jonathan Rose Guy Lemieux University of Toronto Toronto ON Canada University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

The battle of fixed function devices vs. programmable devices has been won by the programmables. The question facing us now is to determine what kinds of programmability to place on next generation systems/devices. Research and development on many applications has shown that different kinds of hardware and software programmability succeed for different application classes: powerful, singlethread-optimized CPUs continue to do very well for many applications; the General Purpose GPU is carving a niche in high throughput, parallel floating point codes in addition to its home turf of graphics; the FPGA is particularly good at variable bit-size computations and data steering, as well as parallel distributed control of networks. Future systems may well need all three types of these types of engines, and perhaps interesting mixtures of them. This is particularly true when we deal with the combined goals of optimizing cost, performance and *** this workshop, we will look to the future of the FPGA within these types of 'converged' programmable computing engines, and reflectively ask ourselves: What role can the FPGA play? What future applications in areas such as networking, mobile, and artificial intelligence can be driven by FPGAs? How do FPGAs fit into the architecture realm of CPUs, general purpose GPUs, and DSPs? How should the designer/programme express their intent in the most effective way possible? What are the requirements for a compilation and optimization environment that allow FPGAs to intermix within a heterogeneous and converged future?The intent of this workshop is to open a discussion on these questions. There will be a series of short, invited talks interspersed with free and open discussion.

关键词： heterogeneity reconfigurable computing high level programming models fpga heterogeneous computing systems signal processing dsp

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Voter insertion algorithms for FPGA designs using triple modular redundancy 10

Voter insertion algorithms for FPGA designs using triple mod...

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18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

作者： Johnson, Jonathan M. Wirthlin, Michael J. Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84606 United States

ISBN: (纸本)9781605589114

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce and contrast four algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks will be reported. This paper will demonstrate that one of the algorithms provides the best overall timing performance results with an average 9.8% increase in critical path length over a triplicated design without voters. Another algorithm provides far better area results at a slightly higher timing cost (an average 2.1% area increase over a triplicated design without voters). Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Bit-level optimization for high-level synthesis and FPGA-based acceleration 10

Bit-level optimization for high-level synthesis and FPGA-bas...

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18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

作者： Zhang, Jiyu Zhang, Zhiru Zhou, Sheng Tan, Mingxing Liu, Xianhua Cheng, Xu Cong, Jason MicroProcessor Research and Development Center Peking University Beijing China Computer Science Department University of California Los Angeles CA 90095 United States PKU/UCLA Joint Research Institute in Science and Engineering China AutoESL Design Technologies Los Angeles CA 90064 United States

ISBN: (纸本)9781605589114

Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and high-level synthesis of algorithmic descriptions may generate suboptimal implementations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting high-level synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. This allows high-level synthesis tools to automatically generate circuits with higher quality. Experiments show that our algorithm can reduce slice usage by 29.8% on average for a set of real-life benchmarks on Xilinx Virtex-4 FPGAs. In the meantime, the clock period is reduced by 13.6% on average, with an 11.4% latency reduction. Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Haptic Rendering of Deformable Objects Using a Multiple FPGA Parallel Computing Architecture 10

Haptic Rendering of Deformable Objects Using a Multiple FPGA...

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18th acm international symposium on field-programmable gate arrays

作者： Mandavikhah, Behzad Mafi, Ramin Sirouspour, Shahin Nicolici, Nicola McMaster Univ Hamilton ON Canada

ISBN: (纸本)9781605589114

High-fidelity simulations of haptic interaction with deformable objects is computationally challenging. In this paper, hardware-based parallel computing is proposed for finite-element (FE) analysis of soft-object deformation models. A distributed implementation of the Preconditioned Conjugate Gradient (PCG) algorithms on N field programmable gate Array (FPGA) devices can solve the large system of equations arising from FE models at high update rates required for stable haptic interaction. Massive parallelization of the computations is achieved by customizing the hardware architecture to the problem at hand and concurrently employing a large number of adaptive fixed-point computing units. An implementation of this scalable hardware accelerator on four Altera EP3SE110 FPGA devices is capable of performing 230.4 Giga Operations per second in Sparse Matrix by Vector (SpMxV) multiplication. This architecture has successfully enabled real-time simulation of haptic interaction with a 3-dimensional FE model of 6000 nodes at an update rate of 200 Hz. Both static and dynamic linear elastic models have been successfully simulated.

关键词： field-programmable gate array (FPGA) Finite-element method (FEM) Conjugate Gradient (CG) Soft-object deformation

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Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

Regular fabric design with ambipolar CNTFETs for FPGA and st...

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2010 IEEE/acm international symposium on Nanoscale Architectures, NANOARCH 2010

作者： De Marchi, Michele Ben Jamaa, M. Haykel De Micheli, Giovanni EPFL Lausanne Switzerland CEA-LETI-MINATEC 17 Rue des Martyrs F-38054 Grenoble France

ISBN: (纸本)9781424480180

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we selected a number of gates with an And-Or-Inverter structure and produced a first comparison with existent medium-grained logic blocks, like the Actel ACT1 and 4-input LUTs [1]. Preliminary evaluation of our gates indicates improvements of around 47% over the ACT1 and of about 18x with respect to 4-input LUTs in terms of areaxnormalized delay. ©2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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The Impact of Interconnect Architecture on Via-Programmed Structured ASICs (VPSAs) 10

The Impact of Interconnect Architecture on Via-Programmed St...

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18th acm international symposium on field-programmable gate arrays

作者： Ahmed, Usman Lemieux, Guy G. F. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781605589114

In this paper, we evaluate the performance of an FPGA-like interconnect fabric for structured ASICs which is based upon fixed metal and programmable vias. We call this type of device a via-programmed structured ASIC or VPSA. We look at two different types of VPSA routing fabrics: one uses jumper wiring and the other uses crossover wiring. The performance of these fabrics is compared against an ASIC-like interconnect fabric, otherwise known as a metal-programmed structured ASIC or MPSA, which can be configured by customizing metal and via layers. We study the impact of these routing fabrics on cost, area, power and delay metrics. The results for different fabrics span a wide range, suggesting the routing architecture plays a very important role in their overall performance and it should be thoroughly researched.

关键词： Structured ASICs Via programmable Fabric

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