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FPGA Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th acm international symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the FPGA interconnect by 14%.

关键词： field-programmable gate arrays FPGAs power optimization low-power design logic synthesis technology mapping

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A 3D-Audio Reconfigurable Processor 10

A 3D-Audio Reconfigurable Processor

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18th acm international symposium on field-programmable gate arrays

作者： Theodoropoulos, Dimitris Kuzmanov, Georgi Gaydadjiev, Georgi Delft Univ Technol Dept Elect Engn Comp Engn Lab NL-2600 GA Delft Netherlands

ISBN: (纸本)9781605589114

Various multimedia communication systems based on 3D-Audio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in the literature follow a PC-based approach that introduces processing bottlenecks and excessive power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware accelerators exploiting the beamforming and the Wave field Synthesis algorithms. The theoretical scalability of the proposed processor is explored with respect to systems consisting of different microphone and loudspeaker arrays configurations. A working FPGA prototype is compared against a software implementation on a Core2 Duo system. Results suggest that the proposed reconfigurable hardware solution can process data up to 2.4x faster than the software approach, while power consumption is approximately 7 Watts according to the Xilinx XPower report.

关键词： 3D-Audio Wave field Synthesis Beamforming Reconfigurable Computing Communication Systems

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3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory 10

3D-NonFAR: Three-dimensional non-volatile FPGA architecture ...

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proceedings of the 16th acm/IEEE international symposium on Low power electronics and design

作者： Chen, Yibo Zhao, Jishen Xie, Yuan Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

ISBN: (纸本)9781450301466

Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero boot-up delay, real-time reconfigurability, and superior energy efficiency. This paper presents a novel threedimensional (3D) non-volatile FPGA architecture (3D-Non- FAR) using phase change memory (PCM) and 3D die stacking techniques. Basic structures in a conventional FPGA architecture are renovated with PCM, and components are repartitioned and reorganized in 3D-NonFAR to allow an efficient 3D integration of PCM elements. 3D-NonFAR not only preserves the advantages of existing non-volatile FPGAs, but also provides high integration density, high performance, and bit-level programmability, which enable PCM as a universal memory replacement in FPGAs. Evaluation results show that 3D-NonFAR has smaller footprint, higher performance, and lower power consumption compared with other FPGA counterparts. Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Design of the data acquisition and real-time imaging system for UIRFPA

Design of the data acquisition and real-time imaging system ...

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5th international symposium on Advanced Optical Manufacturing and Testing Technologies - Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology

作者： Pan, Taoli Xie, Guangzhong Zhou, Yun Jiang, Yadong Wu, Zhiming Univ Elect Sci & Technol China Sch Optoelect Informat State Key Lab Elect Thin Films & Integrated Devic Chengdu 610054 Peoples R China

ISBN: (纸本)9780819480880

This paper presents a useful design of the time-series driving, data acquisition and real-time imaging system for the uncooled infrared focal plane arrays (UIRFPA). The field programmable gate array (FPGA) is used as the central processing unit (CPU) in the system, which can control and harmonize all functional modules. The Ping-Pong structure is employed to realize real-time imaging. The SDRAM is adopted for the data storage to fulfill the need of mass memory. And there are also some switches and keys to provide human-machine interaction. This system works for UIRFPA with resolution of 320x240 steadily and authoritatively. The noise doesn't merge in main signals, so the system can extract the signals of UIRFPA accurately and efficiently.

关键词： uncooled infrared focal plane arrays data acquisition real-time imaging field programmable gate array

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FPGA 2008 - Sixteenth acm/sigda international symposium on field-programmable gate arrays

FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on F...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

ISBN: (纸本)9781595939340

The proceedings contain 24 papers. The topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for FPGAs on commodity hardware;enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals;mapping for better than worst-case delays in LUT-based FPGA designs;a complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs;efficient ASIP design for configurable processors with fine-grained resource sharing;pattern-based behavior synthesis for FPGA resource reduction;modeling routing demand for early-stage FPGA architecture development;and trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.

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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2008年 iii页

作者： Hutton, Mike Chow, Paul University of Toronto

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FPGA implementation of highly parallelized decoder logic for network coding (abstract only) 10

FPGA implementation of highly parallelized decoder logic for...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunwoo Kim Won W. Ro Yonsei University Seoul South Korea

ISBN: (纸本)9781605589114

Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmable gate-array (FPGA). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. The decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. The performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.

关键词： network coding fpga fpga implementation galois field arithmetic

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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Scalable architecture for programmable quantum gate array (abstract only) 10

Scalable architecture for programmable quantum gate array (a...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Mingjie Lin Yaling Ma UC Berkeley Berkeley CA USA UC Berkeley Berkeley USA

ISBN: (纸本)9781605589114

This work explores architectural ideas to build a scalable programmable quantum gate array (PQGA) by exploiting unique quantum effects such as superposition and entanglement/teleportation. In contrast to prior studies, in which a quantum computing machine is implemented either as an ASIC-like special-purpose chip tailored for specific algorithm or as a general-purpose processor based on the Von-Neumann model, we propose a PQGA architecture that is reconfigurable for different domain-specific applications with high logic density. The PQGA architecture is novel in several aspects, among which its interconnect work is built with "virtual wires" implemented with quantum entanglement. In this work, we propose various designs for logic block, interconnect network, and design strategies to construct large designs in PQGA. Our goal is to investigate new architectural ideas based on reconfigurable computing method in order to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum comput- ing. Leveraging the extensive groundwork in quantum computing and algorithm design, we provide estimation results to show that our proposed PQGA architecture can achieve not only high performance but also scalability. Finally, we benchmark our proposed PQGA architecture against previous quantum computer architecture and illustrate on average a 3x improvement in terms of logic density for the well-known Shor's quantum factoring algorithm.

关键词： reconfigurable computing quantum

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