The proceedings contain 24 papers. The topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for FPGAs on commodity hardware;enforcing long-path timing closure for...
ISBN:
(纸本)9781595939340
The proceedings contain 24 papers. The topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for FPGAs on commodity hardware;enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals;mapping for better than worst-case delays in LUT-based FPGA designs;a complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs;efficient ASIP design for configurable processors with fine-grained resource sharing;pattern-based behavior synthesis for FPGA resource reduction;modeling routing demand for early-stage FPGA architecture development;and trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
The proceedings contain 34 papers. The topics discussed include: FPGA prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on FPGAs;energy efficient s...
ISBN:
(纸本)9781605589114
The proceedings contain 34 papers. The topics discussed include: FPGA prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on FPGAs;energy efficient sensor node implementations;high throughput and large capacity pipelined dynamic search tree on FPGA;FPMR: MapReduce framework on FPGA: a case study of RankBoost acceleration;Axel: a heterogeneous cluster with FPGAs and GPUs;building a faster Boolean matcher using bloom filter;scalable network virtualization using FPGAs;maximizing area-constrained partial fault tolerance in reconfigurable logic;FPGA based chip emulation system for test development and verification of analog and mixed signal circuits;a semi-automatic Toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning;and a dependency graph based methodology for parallelizing HLL applications on FPGA.
The proceedings contain 35 papers. The topics discussed include: using source-level transformations to improve high-level synthesis debug and validation on fpgas;high-level design tools for floating point FPGAs;softwa...
ISBN:
(纸本)9781450333153
The proceedings contain 35 papers. The topics discussed include: using source-level transformations to improve high-level synthesis debug and validation on fpgas;high-level design tools for floating point FPGAs;software-driven hardware development;InTime: a machine learning approach for efficient selection of FPGA CAD tool parameters;enhancing hardware design flows with MyHDL;rapid prototyping of wireless physical layer modules using flexible software/hardware design flow;application of specific delay window routing for timing optimization in FPGA designs;application of specific delay window routing for timing optimization in FPGA designs;fine-grained interconnect synthesis;delay-bounded routing for shadow registers;EURECA: on-chip configuration generation for effective dynamic data access;energy-efficient discrete signal processing with fieldprogrammable analog arrays (FPAAs);expanding OpenFlow capabilities with virtualized reconfigurable hardware.
The proceedings contain 23 papers. The topics discuss include: CompressedLUT: an open-source tool for lossless compression of lookup tables for function evaluation and beyond;MiCache: an MSHR-inclusive non-blocking ca...
ISBN:
(纸本)9798400704185
The proceedings contain 23 papers. The topics discuss include: CompressedLUT: an open-source tool for lossless compression of lookup tables for function evaluation and beyond;MiCache: an MSHR-inclusive non-blocking cache design for FPGAs;Hardcaml MSM: a high-performance split CPU-FPGA multi-scalar multiplication engine;DynaRapid: from C to FPGA in a few seconds;design and implementation of a primary visual cortex pathway model based on opponent-process theory;Hardcaml: an OCaml hardware domain-specific language for efficient and robust design;XUNI: virtual machine abstraction for self-contained and multi-tenant cloud FPGAs;ISO-TENANT: rethinking FPGA power distribution network (PDN): a hardware based solution for remote power side channel attacks in FPGA;and accelerating autonomous path planning on FPGAs with sparsity-aware HW/SW co-optimizations.
The proceedings contain 37 papers. The topics discussed include: comparing FPGA vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: autom...
ISBN:
(纸本)9781450305549
The proceedings contain 37 papers. The topics discussed include: comparing FPGA vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: automatic memory and cache management for reconfigurable logic;NETTM: faster and easier synchronization for soft multicores via transactional memory;LegUp: high-level synthesis for FPGA-based processor/accelerator systems;automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs;Torc: towards an open-source tool flow;FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting;a platform for high level synthesis of memory-intensive image processing algorithms;energy-efficient specialization of functional units in a coarse-grained reconfigurable array;and DEEP: an iterative FPGA-based many-core emulation system for chip verification and architecture research.
The proceedings contain 30 papers. The topics discussed include: fast and effective placement and routing directed high-level synthesis for FPGAs;optimizing effective interconnect capacitance for FPGA power reduction;...
ISBN:
(纸本)9781450326711
The proceedings contain 30 papers. The topics discussed include: fast and effective placement and routing directed high-level synthesis for FPGAs;optimizing effective interconnect capacitance for FPGA power reduction;towards interconnect-adaptive packing for FPGAs;modular multi-ported SRAM-based memories;scalable multi-access flash store for big data analytics;cad and routing architecture for interposer-based multi-FPGA systems;memory block based scan-BIST architecture for application-dependent FPGA testing;FPGA-based biophysically-meaningful modeling of olivocerebellar neurons;square-rich fixed point polynomial evaluation on FPGAS;a power side-channel-based digital to analog converter for Xilinx FPGAs;MORP: MakeSpan optimization for processors with an embedded reconfigurable fabric;a scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-BLAs on FPGAs;and Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization.
The proceedings contain 31 papers. The topics discussed include: memory-efficient fast Fourier transform on streaming data by fusing permutations;DeltaRNN: a power-efficient recurrent neural network accelerator;degree...
ISBN:
(纸本)9781450356145
The proceedings contain 31 papers. The topics discussed include: memory-efficient fast Fourier transform on streaming data by fusing permutations;DeltaRNN: a power-efficient recurrent neural network accelerator;degree-aware hybrid graph traversal on FPGA-HMC platform;architecture exploration for HLS-oriented FPGA debug overlays;graph-theoretically optimal memory banking for stencil-based computing kernels;ADAM: automated design analysis and merging for speeding up FPGA development;high-performance QR decomposition for FPGAs;a HOG-based real-time and multi-scale pedestrian detector demonstration system on FPGA;combined spatial and temporal blocking for high-performance stencil computation on FPGAs using OpenCL;P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs;a scalable approach to exact resource-constrained scheduling based on a joint SDC and SAT formulation;dynamically scheduled high-level synthesis;and a customizable matrix multiplication framework for the Intel HARPv2 Xeon+FPGA platform.
The proceedings contain 33 papers. The topics discussed include: flexible communication avoiding matrix multiplication on FPGA with high-level synthesis;maximizing the serviceability of partially reconfigurable FPGA s...
ISBN:
(纸本)9781450370998
The proceedings contain 33 papers. The topics discussed include: flexible communication avoiding matrix multiplication on FPGA with high-level synthesis;maximizing the serviceability of partially reconfigurable FPGA systems in multi-tenant environment;fingerprinting cloud FPGA infrastructures;massively simulating adiabatic bifurcations with FPGA to solve combinatorial optimization;high-performance FPGA network switch architecture;using OPENCL to enable software-like development of an FPGA-accelerated biophotonic cancer treatment simulator;energy-efficient 360-degree video rendering on FPGA via algorithm-architecture co-design;real-time spatial 3D audio synthesis on FPGAS for blind sailing;when massive GPU parallelism ain't enough: a novel hardware architecture of 2D-LSTM neural network;and light-OPU: an FPGA-based overlay processor for lightweight convolutional neural networks.
暂无评论