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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是301-310 订阅

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Flexible multi-mode embedded floating-point unit for field programmable gate arrays

Flexible multi-mode embedded floating-point unit for field p...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Chong, Yee Jern Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605584102

Performance of field programmable gate arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floatingpoint units on FPGAs consume a large amount of resources. This makes FPGAs less attractive for use in floating-point intensive applications. Therefore, there is a need for embedded floating-point units (FPUs) in FPGAs. However, if unutilized, embedded FPUs waste space on the FPGA die. To overcome this issue, we propose a flexible multi-mode embedded FPU for FPGAs that can be configured to perform a wide range of operations. The floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on our FPGA with embedded FPU blocks. The results using our embedded FPUs showed a mean area improvement of 5.2 times and a mean delay improvement of 5.8 times for the doubleprecision benchmarks, and a mean area improvement of 4.4 times and a mean delay improvement of 4.2 times for the single-precision benchmarks. Copyright 2009 acm.

关键词： Adders

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A 17ps time-to-digital converter implemented in 65nm technology

A 17ps time-to-digital converter implemented in 65nm technol...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Favi, Claudio Charbon, Edoardo École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781605584102

This paper presents a new architecture for time-to-digital enabling a time resolution of 17ps over a range 50ns with a conversion rate of 20MS/s. The proposed , implemented in a 65nm FPGA system, consists a pipelined interpolating time-to-digital converter (TDC). The TDC comprises a coarse time discriminator and ne delay line, capable of sustained operation at a clock of 300MHz. A Turbo version of the circuit implements pipelined interpolating TDC with suppressed dead to reach a conversion rate of 300MS/s at the expense a systematic asymmetry that requires fast error correction. TDCs proposed in this paper can be compensated process, voltage, and temperature (PVT) variations using conventional charge pump based feedback or a digital technique. Results demonstrate the suitability the approach for a variety of applications involving precision ultra-fast time discrimination, such as optical sensing, time-of-ight cameras, high throughput comlinks, RADARs, etc. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Fast and scalable packet classification using perfect hash

Fast and scalable packet classification using perfect hash

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Puš, Viktor Korenek, Jan CESNET z. s. p. o. Zikova 4 160 00 Prague Czech Republic Faculty of Information Technology Brno University of Technology Bozetechova 2 612 66 Brno Czech Republic

ISBN: (纸本)9781605584102

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them cancompete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Towards reliable 5Gbps wave-pipelined and gbps surfing interconnect in 65nm FPGAs

Towards reliable 5Gbps wave-pipelined and gbps surfing inter...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Teehan, Paul Lemieux, G.F. Greenstreet, R. Dept. of ECE University of British Columbia Canada Dept. of Computer Science University of British Columbia Canada

ISBN: (纸本)9781605584102

FPGA user clocks are slow enough that only a fraction of the interconnect's is actually used. There may be an opportunity use throughput-oriented interconnect to decrease routing and wire area using on-chip serial signaling, especially datapath designs which operate on words instead of bits. To so, these links must operate reliably at very high bit rates. We wave pipelining and surfing source-synchronous schemes the presence of power supply and crosstalk noise. In particular, noise is a critical modeling challenge;better models are for FPGA power grids. Our results show that wave pipelining operate at rates as high as 5Gbps for short links, but it is sensitive to noise in longer links and must run much slower to reliable. In contrast, surfing achieves a stable operating bit rate of 3Gbps and is relatively insensitive to noise. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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FPCNA: A field programmable carbon nanotube array

FPCNA: A field programmable carbon nanotube array

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Dong, Chen Chilstedt, Scott Chen, Deming Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign Urbana-Champaign United States

ISBN: (纸本)9781605584102

Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architecture known as FPCNA. We define novel CNT and nanoswitch based components and characterize these components considering nanospecific process variations, including the variation caused by the random mixture of metallic and semiconducting CNTs. To evaluate the architecture, we develop a variation-aware physicaldesign flow which can handle both Gaussian and non-Gaussian random variables using variation-aware placement and routing. When FPCNA is evaluated with this CAD flow, we see a 2.67 performance gain over a baseline CMOS FPGA at the same technology node (at a 95% performance yield). In addition, FPCNA offers a 4.5 footprint reduction compared to the baseline FPGA. These results demonstrate the potential of using CNTs and nanoswitches to build high performance FPGA circuits. Copyright 2009 acm.

关键词： Carbon nanotubes

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A comparison of CPUs, GPUs, FPGAs, and massively processor arrays for random number generation

A comparison of CPUs, GPUs, FPGAs, and massively processor a...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Thomas, David B. Howes, Lee Luk, Wayne Imperial College London United Kingdom

ISBN: (纸本)9781605584102

The future of high-performance computing is likely to rely the ability to efficiently exploit huge amounts of paral- . One way of taking advantage of this parallelism is formulate problems as "embarrassingly parallel" Monte- simulations, which allow applications to achieve a lin- speedup over multiple computational nodes, without re- a super-linear increase in inter-node communication. , such applications are reliant on a cheap supply high quality random numbers, particularly for the three maximum entropy distributions: uniform, used as a source of randomness;Gaussian, for discrete-time;and exponential, for discrete-event simulations. this paper we look at four different types of platform: multi-core CPUs (Intel Core2);GPUs (NVidia 200);FPGAs (Xilinx Virtex-5);and Massively Paral- Processor arrays (Ambric AM2000). For each platform determine the most appropriate algorithm for generat- each type of number, then calculate the peak generation rate and estimated power efficiency for each device. Copyright 2009 acm.

关键词： Graphics processing unit

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SmartOpt: An industrial strength framework logic synthesis

SmartOpt: An industrial strength framework logic synthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jang, Stephen Wu, Dennis Jarvin, Mark Chan, Billy Chung, Kevin Mishchenko, Alan Brayton, Robert Xilinx Inc United States University of California Berkeley United States

ISBN: (纸本)9781605584102

In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial FPGAs. This paper presents a framework (SmartOpt) for mapping complex FPGA architectures to a simple netlist model, which can be supported by academic tools. SmartOpt was applied to leverage the algorithms implemented in the ABC package and to study their relative contributions. This work is integrated into the Xilinx ISE 11.1 software flow for FPGAs and shows significant improvements in both the LUT count and performance of large industrial circuits described in HDL. Xilinx Synthesis Technology (XST) reference flow was compared experimentally against the same flow augmented by SmartOpt. When applied to a set of 20 large industrial Virtex-5 benchmarks ranging from 17K to 69K 6- LUTs, the augmented flow produced 8.3% fewer LUTs and led to 2.1% higher operating frequency while keeping runtimes reasonable. With dual-LUT-merging, the LUT count is reduced by 22.7%, while increasing the operating frequency only by 0.7%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Towards automated ECOs in FPGAs

Towards automated ECOs in FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Andrew Brown, Stephen Zhu, Jianwen Safarpour, Sean Electrical and ComputerEngineering University of Toronto Canada Toronto Technology Center Altera Corporation Canada

ISBN: (纸本)9781605584102

During the FPGA design flow, engineering change orders (ECOs) have become an essential methodology to apply late-stage specification changes and bug fixes. ECOs are beneficial since they are applied directly to a place-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which has an unpredictable impact on the design's final correctness and end costs. As a solution, we introduce an automated method to tackle the ECO problem. Specifically, we introduce a resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design;thereby removing the inefficient manual effort required by a designer. Our technique is robust enough to handle a wide range of changes. Furthermore, our technique can successfully make late-stage functional changes while minimally perturbing the place-and-routed netlist: something that is necessary for ECOs. When applied to several benchmarks on Altera's Stratix architecture, we show that our approach can automatically apply ECOs in over 80% of the cases presented. Furthermore, our technique does this with a minimal impact to the circuit performance where on average over 90% of the placement and routing wires remain unchanged. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Choose-your-own-adventure routing: Lightweight load-time defect avoidance

Choose-your-own-adventure routing: Lightweight load-time def...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Rubin, Raphael DeHon, André Computer and Information Science University of Pennsylvania 3330 Walnut Street Philadelphia PA 19104 United States Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd Street Philadelphia PA 19104 United States

ISBN: (纸本)9781605584102

Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. The fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable hannel width, routes can tolerate 0.01% switch defect rates, raising yield from essentially 0% to near 100%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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A high-performance FPGA architecture for restricted machines

A high-performance FPGA architecture for restricted machines

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ly, Daniel L. Chow, Paul Department of Electrical and Computer Engineering University of Toronto Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781605584102

ef>Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of is due to the fact that neural networks are usually as software running on general-purpose processors. to implement a neural network in software typically O(n2) problems - as a result, neural networks unable to provide the performance and scalability required non-academic settings. this paper, we investigate how FPGAs can be used take advantage of the inherent parallelism in neural networks provide a better implementation in terms of scalability performance. We will focus on the Restricted machine, a popular type of neural network, because architecture is particularly well-suited to hardware . The proposed, multi-purpose hardware framework designed to reduce the O(n2) problem into an O(n) implementation only requiring O(n) resources. The framework tested on a Xilinx Virtex II-Pro XC2VP70 FPGA at 100MHz. The resources support a Restricted machine of 128 x 128 nodes, which results in computational speed of 1.02 billion connection-updatesper- and a speed-up of 35 fold over an optimized C program running on a 2.8GHz Intel processor. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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