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Scalable don't-care-based logic optimization and resynthesis

Scalable don't-care-based logic optimization and resynthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Mishchenko, Alan Brayton, Robert Jiang, Jie-Hong Roland Jang, Stephen Department of EECS University of California Berkeley United States Department of EE National Taiwan University Taiwan Xilinx Inc. San Jose CA United States

ISBN: (纸本)9781605584102

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't cares computed for a window surrounding a node and can take into account external don't cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT count and logic level is reduced by 11.8% and 16.5%, respectively. Experimental results on 6-input LUT networks after high-effort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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High-performance, energy-efficient platforms in-socket FPGA accelerators

High-performance, energy-efficient platforms in-socket FPGA ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Liu Oliver, Neal Bhushan, Chitlur Qigang, Wang Chen, Alvin Wenbo, Shen Zhihong, Yu Sheiman, Arthur McCallum, Ian Grecco, Joseph Mitchel, Henry Dong, Liu Gupta, Prabhat Intel Corporation

ISBN: (纸本)9781605584102

Growing demand for energy-efficient, high-performance systems has resulted in the growth of innovative heterogeneous computing system architectures that use FPGAs. FPGA-based architectures enable designers to implement custom instruction streams executing on potentially thousands of compute elements. Traditionally, FPGAs have been used as compute elements on PCI devices;however, this does not allow the FPGAs to be coprocessors. This paper describes a high-performance system architecture that is based on the Intel Xeon platform in which one or more FPGAs, acting as application accelerators, replace one or more processors in a dual/multi-processor (DP/MP) platform. The FPGA is thus connected directly to the Front Side Bus (FSB) and enjoys the same privileges as a processor, i.e., full participation in the coherency protocol, unrestricted access to system memory and to other processors via the high bandwidth, and low latency connection to the FSB. In addition, we also describe a software layer called the "Accelerator Abstraction Layer (AAL)", which provides a uniform, hardware- and/or platform-independent application interface. Applications written on AAL can be ported to multiple platforms that have different types of accelerators and the application does not have to be modified. In addition, the AAL also enables the developer/user to reprogram the FPGA on the fly (analogous to an operating system context switch) thereby utilizing the programmable nature of the FPGA. The resulting hardware/software stack creates a flexible and powerful platform for accelerator innovation and deployment. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Large-scale wire-speed packet classification on FPGAs

Large-scale wire-speed packet classification on FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jiang, Weirong Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)9781605584102

Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Although a plethora of research has been done in this area, wire-speed packet classification while supporting large rule sets remains difficult. This paper exploits the features provided by current FPGAs and proposes a decision-tree-based, two-dimensional dual-pipeline architecture for multi-field packet classification. To fit the current largest rule set in the on-chip memory of the FPGA device, we propose several optimization techniques for the stateof- the-art decision-tree-based algorithm, so that the memory requirement is almost linear with the number of rules. Specialized logic is developed to support varying number of branches at each decision tree node. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization. Since our architecture is linear and memory based, on-the-fly update without disturbing the ongoing operations is feasible. The implementation results show that our architecture can store 10K real-life rules in on-chip memory of a single Xilinx Virtex-5 FPGA, and sustain 80 Gbps (i.e. 2 OC-768 rate) throughput for minimum size (40 bytes) packets. To the best of our knowledge, this work is the first FPGA-based packet classification engine that achieves wire-speed throughput while supporting 10K unique rules. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

VPR 5.0: FPGA CAD and architecture exploration tools with si...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Luu, Jason Kuon, Ian Jamieson, Peter Campbell, Ted Ye, Andy Fang, Wei Mark Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

The VPR toolset [6, 7] has been widely used to perform FPGA architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern FPGAs. This paper describes a new version of the toolset that includes four significant features: first, it now supports a broad range of single-driver routing architectures [29, 4, 16]. Single-driver routing has significantly different architectural and electrical properties from the multi-driver approach previously modelled, and is now employed in the majority of FPGAs sold. Second, the new release can now model a heterogeneous selection of hard logic blocks, which could include the hard memory and multipliers that are now ubiquitous in FPGAs. Third, we provide optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture. Prior releases of VPR did not publish even one architecture file with accurate resistance and capacitance parameters. Finally, to maintain robustness and to support future development the release includes a set of regression tests to check functionality and quality of result of the output of the tools. To illustrate the use of the new features, we present a new look at the FPGA area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design and single-driver architectures, have better area (relative to 4-LUTs) than previously thought. Another experiment shows that several of the previous architectural results are invariant in moving from multi-driver to single-driver routing architecture and across a range of process technologies. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Intel atom processor core made FPGA-synthesizable

Intel atom processor core made FPGA-synthesizable

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Wang, Perry H. Collins, Jamison D. Weaver, Chris T. Kuttanna, Belliappa Salamian, Shahram Chinya, Gautham N. Schuchman, Ethan Schilling, Oliver Doil, Thorsten Steibl, Sebastian Wang, Hong Microarchitecture Research Lab Corporate Technology Group Intel Corporation Atom Processor Architecture Mobility Group Intel Corporation Germany Microprocessor Lab Corporate Technology Group Intel Corporation Germany

ISBN: (纸本)9781605584102

We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with FPGA-synthesizable counterparts. Additionally, as the target FPGA emulator is hosted on a PC platform with the Pentium-based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 FPGA. The synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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Architectural Improvements for field programmable Counter arrays: Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs 08

Architectural Improvements for Field Programmable Counter Ar...

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16th acm/sigda international symposium on field-programmable gate arrays

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Brisk, Philip Gurkaynak, Frank K. Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Inst Microelect & Microsyst Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

The field programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the FPGA. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.

关键词： FPGA field programmable Counter Array (FPCA)

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Architecture-Specific Packing for Virtex-5 FPGAs 08

Architecture-Specific Packing for Virtex-5 FPGAs

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16th acm/sigda international symposium on field-programmable gate arrays

作者： Ahmed, Taneem Kundarewich, Paul D. Anderson, Jason H. Taylor, Brad L. Aggarwal, Rajat Xilinx Inc Toronto ON Canada

ISBN: (纸本)9781595939340

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA - the Xilinx (R) Virtex (TM) -5 FPGA. Two aspects of packing are discussed: 1) packing for general logic blocks, and 2) packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs call implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT Output is associated with slower speed, and therefore, must be used judiciously. We present placement-based techniques for dual-output LUT packing that;lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance.

关键词： field-programmable gate arrays FPGAs optimization packing placement power performance

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A novel FPGA logic block for improved arithmetic performance 08

A novel FPGA logic block for improved arithmetic performance

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Parandeh-Afshar, Hadi Brisk, Philip Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 compared to adder trees synthesized using ternary adders. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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TORCH: A design tool for routing channel segmentation in FPGAs 08

TORCH: A design tool for routing channel segmentation in FPG...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Lin, Mingjie Gamal, Abbas El Department of Electrical Engineering Stanford University CA 94305 United States

ISBN: (纸本)9781595939340

A design tool for routing channel segmentation in island-style FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing channel segmentation using the average interconnect power-delay product as a performance metric, which is estimated from placed and routed designs. A simulated- annealing procedure is used, whereby segmentation is incrementally changed in each iteration, the benchmark designs are mapped using VPR, and the performance metric is computed to decide whether to accept or reject the new segmentation. Run time is signi cantly reduced by using incremental routing in each iteration and parallelizing the metric evaluation. Experimental results using the MCNC benchmark designs demonstrate an average of 22% and 15% reduction in delay and power relative to a baseline segmentation. The results also show that average segment length should decrease with technology scaling. Finally, we demonstrate how the tool can be used to optimize other aspects of programmable routing in an FPGA. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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