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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Dalal, Ishaan L. Stefan, Deian Dept. of Electrical Engineering Cooper Union New York NY 10003 United States

ISBN: (纸本)9781595939340

Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality pseudo-random number generators (PRNG), such as the Mersenne Twister, are often based on binary linear recurrences and have extremely long periods (more than 21024). Many software implementations of such PRNGs exist, but hardware implementations are rare. We have developed an optimized, resource-efficient parallel framework for this class of random number generators that exploits the underlying algorithm as well as FPGA-specific architectural features. The framework also incorporates fast "jump-ahead" capability for these PRNGs, allowing simultaneous, independent sub-streams to be generated in parallel by partitioning one long-period pseudorandom sequence. We demonstrate parallelized implementations of three types of PRNGs - the 32-, 64- and 128-bit SIMD Mersenne Twister - on Xilinx Virtex-II Pro FPGAs. Their area/throughput performance is impressive: for example, compared clock-for-clock with a previous FPGA implementation, a "two-parallelized" 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350 MHz for a throughput of 22.4 Gbps, which is 5.5x faster than the older FPGA implementation and 7.1x faster than a dedicated software implementation. The quality of generated random numbers is verified with the standard statistical test batteries diehard and TestU01. We also present two real-world application studies with multiple RNG streams: the Ziggurat method for generating normal random variables and a Monte Carlo photon-transport simulation. The availability of fast long-period random number generators with multiple streams accelerates hardware-based scientific simulations and allows them to scale to greater complexities. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Placement Challenges for Structured ASICs 08

Placement Challenges for Structured ASICs

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acm international symposium on Physical Design

作者： Schmit, Herman Gupta, Amit Ciobanu, Radu eEASIC Corp 2585 Augustine Ave Santa Clara CA 95054 USA Easic Corp Iasi Romania

ISBN: (纸本)9781605580487

The placement problem for structured ASICs combines aspects of the standard cell ASIC placement problem and FPGA placement. Similarities with ASIC placement include the number and size of the place-able objects and the need to consider buffering within placement. Similarities with FPGA placement include the existence of discrete legal locations for all types of objects, the constraints caused by "intrinsic" connections, such as clock, reset or 10 signals and fixed routing tracks. The research community has provided detailed analysis of various different solutions for the standard cell placement problem over the last two decades. FPGA placement research has not focused on the legalization issues. Architecturally, FPGAs are changing to focus more on synthesis and clustering than fine-grained placement to meet timing. In this paper we discuss the similarities and differences between FPGA, Standard Cell, and Structured ASIC placement, and we present new representations and tests cases for the structured ASIC problem.

关键词： field programmable gate arrays Placement Structured ASICs

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Full-system chip multiprocessor power evaluations using FPGA-based emulation

Full-system chip multiprocessor power evaluations using FPGA...

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ISLPED'08: 13th acm/IEEE international symposium on Low Power Electronics and Design

作者： Bhattacharjee, Abhishek Contreras, Gilberto Martonosi, Margaret Department of Electrical Engineering Princeton University

ISBN: (纸本)9781605581095

The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS, Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35 X speedup compared to full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Amplifying embedded system efficiency via automatic instruction fusion on a post-manufacturing reconfigurable architecture platform

Amplifying embedded system efficiency via automatic instruct...

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9th international symposium on Quality Electronic Design

作者： Cheng, Allen C. Univ Pittsburgh Adv Comp Technol Lab Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9780769531175

Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability;while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM;FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible Versatile Processing Unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.

关键词： field programmable gate arrays (FPGA)

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Fourteenth acm/sigda international symposium on field programmable gate arrays - FPGA 2006

Fourteenth ACM/SIGDA International Symposium on Field Progra...

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

ISBN: (纸本)1595932925

The proceedings contain 22 papers. The topics discussed include: embedded floating-point units in FPGAs;measuring the gap between FPGAs and ASICs;optimality study of logic synthesis for LUT-based FPGAs;improvements to technology mapping for LUT-based FPGAs;improving performance and robustness of domain-specific CPLDs;design, implementation, and verification of active cache emulator (ACE);modeling and data-dependent performance of pattern-matching architectures;yield enhancements of design-specific FPGAs;FGPA clock network architecture: flexibility vs. area and power;a reconfigurable hardware based embedded scheduler for buffered crossbar switches;and combining module selection and resource sharing for efficient FPGA pipeline synthesis.

关键词： field programmable gate arrays

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Efficient tiling patterns for reconfigurable gate arrays 08

Efficient tiling patterns for reconfigurable gate arrays

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proceedings of the 16th international acm/sigda symposium on field programmable gate arrays

作者： Sumanta Chaudhuri Jean-Luc Danger Philippe Hoogvorst Sylvain Guilley ENST Paris France

ISBN: (纸本)9781595939340

This article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in FPGAs. The goal of our research is to evolve FPGA architectures with advances in technology, and specifically better utilization of available interconnect layers. We propose a method to evaluate tiling patterns based on the first principles ( i.e Rent's Rule, Donath's result, equivalence of wire flux and wire length). We show that, use of tiling patterns formed with higher order polygons can improve the speed and area performances of an FPGA. This gain is highly dependent on depopulation schemes and other parameters. However for generic tiling patterns with crossbar switchboxes there is a 22% gain in area for the hexagonal tiling pattern, and a 30% gain in area for the octagonal tiling pattern. Moreover the average interconnect length is around 15% lesser for hexagonal and 31% lesser for the octagonal tiling compared to square tiling. We can expect a proportional increase in speed. We also present a comparative plot of total interconnect lengths for these tiling patterns and the hierarchical gate arraysThe physical realizability of these tiling patterns in CMOS are to be investigated. We present a layout scheme for both hexagonal and octagonal FPGAs. To our knowledge standard processes support 45° metal lines, whereas 60° lines can be etched using non-standard processes. We must keep in mind, that in practice one must use some sort of depopulation and staggering scheme, and these results provide only an idea of gains that can be achieved. The actual interconnect structure is of course dependent on several factors (i.e available interconnect layers, difficulty of fabrication, required speed/area, evolution of CMOS technology etc). Our future research direction will be to choose an efficient interconnect strategy based on this and previous researches, as well as experimental results

关键词： tiling interconnect FPGA hexagonal octagonal

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2006年 iii页

作者： Wilton, Steve DeHon, Andre University of British Columbia Canada California Institute of Technology United States

No abstract available

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A Synthesizable Datapath-Oriented Embedded FPGA Fabric 07

A Synthesizable Datapath-Oriented Embedded FPGA Fabric

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Wilton, Steve J. E. Ho, C. H. Leong, Philip H. W. Luk, Wayne Quinton, Brad Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

We present an architecture for a synthesizable datapath-oriented field programmable gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.

关键词： field programmable gate Array Datapath Synthesis Integrated Circuit System-on-Chip Embedded Block

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GlitchLess: An Active Glitch Minimization Technique for FPGAs 07

GlitchLess: An Active Glitch Minimization Technique for FPGA...

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Lamoureux, Julien Lemieux, Guy G. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow.

关键词： field-programmable gate arrays Power Minimization

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Design of a Logic Element for Implementing an Asynchronous FPGA 07

Design of a Logic Element for Implementing an Asynchronous F...

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Smith, Scott C. Univ Missouri Dept Elect & Comp Engn Rolla MO 65462 USA

ISBN: (纸本)9781595936004

A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.

关键词： Asynchronous logic design delay-insensitive circuits field programmable gate Array (FPGA) NULL Convention Logic (NCL) reconfigurable logic

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