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Reconfigurable Finite field Instruction Set Architecture

Reconfigurable Finite Field Instruction Set Architecture

引用

15th acm/sigda international symposium on field-programmable gate arrays

作者： Jachimiec, Nathan Martinez-Vallina, Fernando Saniie, Jafar IIT Embedded Comp & Signal Proc Res Grp Chicago IL 60616 USA

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex(2)Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2(163)) multiplier, a speed-up factor of 1530x has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： Finite field Arithmetic Galois fields Instruction Set Extensions Xilinx MicroBlaze Fast Simplex Links FSL Embedded Development Partial Reconfiguration

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FPGA 2001: Fifteenth acmIsigda international symposium on field-programmable gate arrays

FPGA 2001: Fifteenth ACMISIGDA International Symposium on Fi...

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FPGA 2007: Fifteenth acm/sigda international symposium on field-programmable gate arrays

ISBN: (纸本)1595936009

The proceedings contain 25 papers. The topics discussed include: a routing fabric for monolithically stacked 3D-FPGA;design of a logic element for implementing an asynchronous FPGA;designing efficient input interconnect blocks for LUT clusters using counting and entropy;a synthesizable datapath-oriented embedded FPGA fabric;a versatile, low latency HyperTransport core;an FPGA-based Pentium in a complete desktop system;a 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA;variation-aware routing for FPGAs;stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation;post-route LUT output polarity selection for timing optimization;synthesis of an application-specific soft multiprocessor system;FPGA-friendly code compression for horizontal microcoded custom IPs;and a practical FPGA-based framework for novel CMP research.

关键词： field programmable gate arrays (FPGA)

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SEU-Mitigation placement and routing algorithms and their impact in SRAM-based FPGAs

SEU-Mitigation placement and routing algorithms and their im...

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8th international symposium on Quality Electronic Design

作者： Zarandi, Hamid R. Miremadi, Seyed G. Pradhan, Dhiraj K. Mathew, Jimson Sharif Univ Technol Dept Comp Engn Tehran Iran Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9780769527956

In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility reductions are cumulative or not when they applied in sequence. We have investigated the effect of S-VPR on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 18% and 12%, respectively. However, it increases critical path delay and power consumptions of the circuits up to 5% and 8%, respectively. This means that without any redundancies, just by means of fault-avoidance method, mitigation of SEU effects would decrease up to 22% significantly and this method is notable compared to previous TMR and DWC mechanisms.

关键词： field programmable gate arrays (FPGA)

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2005 acm/sigda Thirteenth international symposium on field-programmable gate arrays

2005 ACM/SIGDA Thirteenth International Symposium on Field-P...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Schmit, Herman Wilton, Steve

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CReconfigurable finite field instruction set architecture 07

CReconfigurable finite field instruction set architecture

引用

proceedings of the 2007 acm/sigda 15th international symposium on field programmable gate arrays

作者： Nathan Jachimie Fernando Martinez-Vallin Jafar Saniie Illinois Institute of Technology Chicago Illinois

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： FSL instruction set extensions Xilinx fast simplex links galois fields MicroBlaze embedded development partial reconfiguration finite field arithmetic

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

ACM/SIGDA Thirteenth ACM International Symposium on Field Pr...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

The proceedings contain 64 papers from the acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005. The topics discussed include: the Stratix II logic and routing architecture;skew-programmable clock design for FPGA and skew-aware placement;sparse matrix-vector multiplication on FPGAs;power modeling and architecture evaluation for FPGA with novel circuits for VDD programmability;architecture adaptive routability-driven placement for FPGAs;energy-efficient FPGA interconnect architecture design;3D-Softchip: A novel 3D vertically integrated adaptive computing system;dynamic reconfiguration in FPGA-based SoC designs;and rapid prototyping of a test harness for forward error correcting codes.

关键词： field programmable gate arrays

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Magnetic tunnelling junction based FPGA 06

Magnetic tunnelling junction based FPGA

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Bruchon, Nicolas Torres, Lionel Sassatelli, Gilles Cambon, Gaston LIRMM 161 rue Ada 34392 Montpellier Cedex 5 France

ISBN: (纸本)1595932925

The aim of this paper is to propose a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM.) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the die. Nevertheless, each configuration memory point has to be readable independently from each other, that is why the approach is different from the classical memory array one. Copyright 2006 acm.

关键词： field programmable gate arrays

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Embedded floating-point units in FPGAs 06

Embedded floating-point units in FPGAs

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Beauchamp, Michael J. Hauck, Scott Underwood, Keith D. Hemmert, K. Scott University of Washington Dept. of Electrical Engineering United States Sandia National Laboratories Scalable Computing Systems United States

ISBN: (纸本)1595932925

Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited the use of FPGAs in scientific applications that require floating-point arithmetic. Even simple floating-point operations consume a large amount of computational resources. In this paper, we introduce embedding floating-point multiply-add units in an island style FPGA. This has shown to have an average area savings of 55.0% and an average increase of 40.7% in clock rate over existing architectures. Copyright 2006 acm.

关键词： field programmable gate arrays

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FPGA clock network architecture: Flexibility vs. area and power

FPGA clock network architecture: Flexibility vs. area and po...

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Lamoureux, Julien Wilton, Steven J. E. Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)1595932925

This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for field-programmable gate arrays (FPGA's). The paper begins by describing a parameterized clock network model that describes a broad range of programmable clock network architectures. Specifically, the model supports architectures with multiple local and global clock domains and varying amounts of flexibility at various levels of the clock network. Using the model, the architectural parameters that control the flexibility of the clock network are varied to determine the cost of this flexibility in terms of area and power dissipation. From these experiments, the study finds that area and power costs are highest for networks with flexibility close to the logic blocks. Furthermore, it found that clock networks with local clock domains have little overhead and are significantly more efficient than clock networks without local clock domains for applications with multiple clocks. Copyright 2006 acm.

关键词： field programmable gate arrays

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An iterative division algorithm for FPGAs 06

An iterative division algorithm for FPGAs

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Liu, Jianhua Chang, Michael Cheng, Chung-Kuan Computer Science and Engineering Department University of California San Diego 92093 United States

ISBN: (纸本)1595932925

Division is one of the most complicated and expensive arithmetic operations. Both clock frequency and operation delay are limited by the memory wall, even in LUT-based FPGA devices. To conquer the memory limitation, we propose a hybrid division algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms. The proposed algorithm boosts very-high radix division efficiently. The algorithm is multiplicative, and feasible for the modern FPGA devices with build-in multipliers. The algorithm is implemented in Altera StratixII FPGA devices and compared with the division IP core generated by Mega Wizard. The result shows that the PST algorithm has higher clock frequency, lower execution time and also lower power consumption. Copyright 2006 acm.

关键词： field programmable gate arrays

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