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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs 02

A flexible floating-point format for optimizing data-paths a...

引用

FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Dido, J. Geraudie, N. Loiseau, L. Payeur, O. Savaria, Y. Poirier, D. Microelectronics Research Group Ecole Polytechnique of Montreal CP 6079 Succ. Centre Ville Montréal Que. H3C 3A7 Canada

ISBN: (纸本)9781581134520

Video signal processing requires complex algorithms performing many basic operations on a video stream. To perform these calculations in real-time in a FPGA, we must use innovative structures to meet speed requirements while managing complexity. As part of a project aiming at the development of a video noise reducer, we developed an optimized processing stream that required some floating-point calculations. This paper presents the rationale for developing a floating-point unit, justifies the data representation used, its implementation in a Xilinx VirtexE FPGA and reports the performance we obtained. A divider using this representation is also presented, with its implementation and performances in the same FPGA.

关键词： field programmable gate arrays

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Circuit design of routing switches 02

Circuit design of routing switches

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Lemieux, Guy Lewis, David Dept. of Electrical and Comp. Eng. University of Toronto Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)9781581134520

This paper examines circuit design of buffered routing switches in symmetrical, island-style FPGAs. The effects of switch size, tile length, level-restoring, and slow input slew rates are examined. Two new fanin-based switch designs are used to eliminate nearly all of the increase in delay that arises from fanout with a previous switch design. Alternating between buffers and pass transistors is shown to improve connection delay without fanout by 25 %. To take advantage of this, we propose schemes to replace some buffers with pass transistors to simultaneously reduce area and delay. Routing a suite of MCNC benchmark circuits shows that 14% in areadelay, or 7% in delay can be saved using the new switch schemes. Alternatively, approximately 13 % in area can be saved with no degradation to delay.

关键词： field programmable gate arrays

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On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques 02

On the sensitivity of FPGA architectural conclusions to expe...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Yan, Andy Cheng, Rebecca Wilton, Steven J.E. Dept. of Elec. and Computer Eng. University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581134520

Recent years have seen a tremendous increase in the capacities and capabilities of field-programmable gate arrays (FPGA's). Much of this dramatic improvement has been the result of changes to the FPGAs' internal architectures. New architectural proposals are routinely generated in both academia and industry. For FPGA's to continue to grow, it is important that these new architectural ideas are fairly and accurately evaluated, so that those worthy ideas can be included in future chips. Typically, this evaluation is done using experimentation. However, the use of experimentation is dangerous, since it requires making assumptions regarding the tools and architecture of the device in question. If these assumptions are not accurate, the conclusions from the experiments may not be meaningful. In this paper, we investigate the sensitivity of FPGA architectural conclusions to experimental variations. To make our study concrete, we evaluate the sensitivity of four previously published and well-known FPGA architectural results: lookup-table size, switch block topology, cluster size, and memory size. It is shown that these experiments are significantly affected by the assumptions, tools, and techniques used in the experiments.

关键词： field programmable gate arrays

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Reliable laser programmable gate array technology 3

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3rd international symposium on Quality Electronic Design

作者： Gao, Z Luo, J Huang, H Zhang, W Bernstein, JB Univ Maryland College Pk MD 20742 USA

ISBN: (纸本)0769515622

field-programmable gate arrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower NRE cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, Laser-induced MakeLink(TM)* technology is proposed as a programmable switch element. The Electrical resistance is as low as 0.8 Omega to 11 Omega, depending on the size of the link, which is 2-3 orders smaller than that of NMOS transistor in a SRAM based FPGA. Thus the speed improvement for Laser field-programmable gate Array (LFPGA) is significant. Other features of Laser-induced vertical links technology, such as small size and radiation hardness, car, also greatly improve the FPGA performance. The cluster-based LFPGA with 128 by 64 basic logic elements (BLE) is laid out under a 0.5 mum commercialized technology. The chip size is about 138mm(2).

关键词： Costs Digital circuits Electric resistance field programmable gate arrays Logic MOSFETs Optical arrays Random access memory Reliability engineering Switches

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Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine

Analysis of quasi-static scheduling techniques in a virtuali...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Markovskiy, Yury Caspi, Eylon Huang, Randy Yeh, Joseph Chu, Michael Wawrzynek, John DeHon, Andreá University of California Berkeley CA United States

The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition of a computation abstracted from the detailed size of the physical hardware. When the number of physical compute pages is smaller than the number of virtual compute pages in the abstract computation graph, the design is time-multiplexed onto the available physical hardware. A key component of this strategy is an automatic scheduler that selects the temporal sequencing of virtual resources onto the physical device. We describe a quasi-static scheduling strategy that retains the full semantic power of the dynamic SCORE flow graph while taking advantage of static scheduling techniques at program load time to hoist most of the computational work out of the inner scheduling loops. This strategy reduces online scheduling work per reconfiguration epoch by an order of magnitude. In addition, a more global perspective available from offline-scheduling improves schedule quality, resulting in a net reduction of total execution time by 46-81%.

关键词： field programmable gate arrays

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A faster distributed arithmetic architecture for FPGAs 02

A faster distributed arithmetic architecture for FPGAs

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Grover, Radhika S. Shang, Weijia Li, Qiang Department of Computer Engineering Santa Clara University Santa Clara CA United States

ISBN: (纸本)9781581134520

Distributed Arithmetic (DA) is an important technique to implement digital signal processing (DSP) functions in FPGAs. However, traditional lookup table (LUT) based DA architectures contain one or more carry propagation chains in the critical path that dictates the fastest time at which an entire design can run. In this paper, we describe a novel technique that can reduce or eliminate the carry-propagate chain from the critical path in LUT based DA architectures on FPGAs. In the proposed scheme, the individual bits of a word do not have to be processed as a unit. Instead, the current iteration can start as soon as the least significant bit (LSB) of the previous iteration is available, without waiting for the entire word from the previous iteration to be fully computed. This technique has great potential in speeding up DSP applications based on DA. Designs are described for serial and parallel DALUT and accumulator structures in which an n-bit carry chain, where n is the word length, is broken into smaller r-bit chains, 1 ≤ r

关键词： field programmable gate arrays

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Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series 02

Timing verification of dynamically reconfigurable logic for ...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Robertson, Ian Irvine, James Lysaght, Patrick Robinson, David Dept. Electronic and Electrical Eng. University of Strathclyde 204 George Street Glasgow G1 1XW United Kingdom

ISBN: (纸本)9781581134520

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.

关键词： field programmable gate arrays

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Application of FPGA technology to accelerate the Finite-Difference Time-Domain (FDTD) method 02

Application of FPGA technology to accelerate the Finite-Diff...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Schneider, Ryan N. Turner, Laurence E. Okoniewski, Michal M. University of Calgary Canada 2500 University Drive NW Calgary Alta. T2N 1N4 Canada

ISBN: (纸本)9781581134520

The continuing advances in the field of electrical engineering, in areas like cellular communications, fiber optics, mobile and multi-gigahertz electronics have necessitated a computer-assisted design approach to the complex electromagnetic interactions and problems that arise. Finite-Difference Time-Domain (FDTD) Analysis is a very powerful tool for the modeling of electromagnetic phenomena. The algorithm is computationally intensive and simulations can run for a few hours to several days. Increasing the computation speed and decreasing the run times of this algorithm would bring greater productivity and new avenues of research to many facets of electrical engineering. The algorithm is transferred to custom FPGA-based hardware using a pipelined bit-serial arithmetic architecture. A one-dimensional resonator is used to verify the implementation and explore the hardware speed and costs. The computational speed is extremely fast and is not related to the number of computational cells in the simulation. Finally, a discussion of future research is presented.

关键词： field programmable gate arrays

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Incremental reconfiguration of multi-FPGA systems 02

Incremental reconfiguration of multi-FPGA systems

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Lee, K.K. Wong, D.F. Synopsys Inc. Mountain View CA United States

ISBN: (纸本)9781581134520

In reconfigurable computing, circuits implemented on multi-FPGA systems have to be incrementally modified. Since reconfiguring an FPGA is time-consuming, the time for reconfiguration depends on the number of FPGAs to be reconfigured. Our objective is to reduce the number of such FPGAs. In this paper, we consider the specific problem of incrementally reconfiguring a multi-FPGA system that utilizes the direct interconnection architecture, where routing connections between FPGAs are to neighbors that are near. This problem can be divided into a net addition problem and a net deletion problem. We show that the net addition problem is a generalization of the NP-complete Steiner tree problem. Our algorithm for this problem is based on an adaptation of the Klein-Ravi approximation algorithm for the node-weighted Steiner tree problem. As for the net deletion problem, we prove that it is NP-complete but the problem is solvable in polynomial time for tree topologies. Based on the algorithm for trees, we design an effective heuristic algorithm for the general net deletion problem. Finally, we present an algorithm for solving the incremental reconfiguration problem which handles both placement of new gates and inter-FPGA routing.

关键词： field programmable gate arrays

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Integrated retiming and placement for field programmable gate arrays 02

Integrated retiming and placement for field programmable gat...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Singh, Deshanand P. Brown, Stephen D. Dept. of Elec. and Computer Eng. University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581134520

Retiming is a synchronous circuit transformation that can optimize the delay of a synchronous circuit by moving registers across combinational circuit elements. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original. In this paper, we address the problem of applying retiming techniques to circuits implemented in field programmable gate arrays (FPGAs). FPGAs contain prefabricated and configurable routing elements that allow us to easily implement a variety of circuits. However this interconnect contributes greatly to the overall delay in the implemented circuit. If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect. Our fundamental experiment is to determine whether there are any gains in tightly coupling retiming and placement so that the retiming algorithm has some estimate of the routing delays. Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features. This retiming algorithm may introduce extra registers into the circuit. These new registers need to be placed in some location in the FPGA. Retiming register placement is accomplished by a novel incremental clustering and placement algorithm. The incremental algorithm builds upon the placement of the non-retimed circuit to intelligently sift in the newly-introduced registers. In addition, we explore making the placement algorithms "retiming aware." These placement algorithms try to place logic blocks in such a way that the subsequent retiming produces better speed results. These techniques include the identification of retiming-critical cycles during placement. Our experiments show that the integration of retiming with placement results in 19% better clock periods in comparison to the application of retiming before the place and route steps.

关键词： field programmable gate arrays

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