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Interconnect pipelining in a throughput-intensive FPGA architecture 01

Interconnect pipelining in a throughput-intensive FPGA archi...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Singh, A. Mukherjee, A. Marek-Sadowska, M. Department of Electrical Engineering University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781581133417

Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, circuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guarantee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput FPGA architecture based on the wavesteering design principle to handle throughput-intensive applications. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined interconnect scheme to support the strict timing requirements that is necessitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this FPGA fabric shows an increasing throughput performance.

关键词： field programmable gate arrays

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An FPGA-based video compressor for H.263 compatible bit streams 01

An FPGA-based video compressor for H.263 compatible bit stre...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lienhart, G. Männer, R. Lay, R. Noffz, K.H. Dept. for Computer Science V University of Mannheim D-68131 Mannheim Germany

ISBN: (纸本)9781581133417

This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

关键词： field programmable gate arrays

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LRoute: A delay minimal router for hierarchical CPLDs 01

LRoute: A delay minimal router for hierarchical CPLDs

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lee, K.K. Wong, M.D.F. Synopsys Inc. 700 E. Middlefield Rd Mountain View CA 94043 United States

ISBN: (纸本)9781581133417

This paper describes LRoute, a novel router for the popular and scalable hierarchical Complex programmable Logic Devoices (CPLDs). CPLD routing has constraints om routing topologies due to architectural limitations and performance considerations. These constraints make the problem quite different from FPGA routing and render the routing problem more complicated. Extensions of popular FPGA routers like the maze router performs poorly on such CPLDs. There is also little published work on CPLD routing. LRoute uses a different paradigm based on the Lagrangian Relaxation framework in the theory of mathematical programming. It respects the topology constraints imposed and routes a circuit with minimum delay. We tested this router on a set of industry problems that commercial software failed to route. Our router was able to route all of them very quickly.

关键词： programmable logic controllers

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Configuration compression for FPGA-based embedded systems 01

Configuration compression for FPGA-based embedded systems

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Dandalis, A. Prasanna, V.K. Electrical Engineering - Systems University of Southern California 3740 McClintock Avenue Los Angeles CA 90089-2562 United States

ISBN: (纸本)9781581133417

FPGAs are a promising technology for developing high-performance embedded systems. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration bit-streams has also increased considerably. As a result, the cost-effectiveness of FPGA-based embedded systems is significantly affected by the memory required for storing various FPGA configurations. This paper proposes a novel compression technique that reduces the memory required for storing FPGA configurations and results in high decompression efficiency. Decompression efficiency corresponds to the decompression hardware cost as well as the decompression rate. The proposed technique is applicable to any SRAM-based FPGA device since configuration bit-streams are processed as raw data. The required decompression hardware is simple and is independent of the individual semantics of configuration bit-streams or specifc features of the on-chip configuration mechanism. Moreover, the time to configure the device is not affected by our compression technique. Using our technique, we demonstrate up to 41% savings in memory for configuration bit-streams of several real-world applications.

关键词： field programmable gate arrays

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Matching and searching analysis for parallel hardware implementation on FPGAs 01

Matching and searching analysis for parallel hardware implem...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Moisset, P. Diniz, P. Park, J. University of Southern California Information Sciences Institute 4676 Admiralty Way Marina del Rey CA 90292 United States

ISBN: (纸本)9781581133417

Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a simple search/matching predicate. Their inherent sequential nature, either because of data dependences but more often because of very strong control dependences, makes it impossible to apply existing data dependence and parallelization analysis to exploit significant levels parallelism on traditional architectures. This paper describes a class of searching and matching computations and describes a mapping strategy to map these computations to hardware. We have developed a compiler analysis in SUIF using array data dependence analysis and implicit loop unrolling analysis to expose more parallelism for the parallel evaluation of these computations. Our compiler generates parallel hardware specifications in VHDL. The resulting parallel hardware yields significant performance improvements when these kernel operators are repeated over shifted portions of the input data on FPGA-based computing architectures.

关键词： field programmable gate arrays

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Performance-driven mapping for CPLD architectures 01

Performance-driven mapping for CPLD architectures

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Chen, D. Cong, J. Ercegovac, M.D. Huang, Z. Department of Computer Science University of California Los Angeles CA 90095 United States

ISBN: (纸本)9781581133417

In this paper we present a performance-driven mapping algorithm, PLAmap, for CPLD architectures which consist of a large number of PLA-style logic cells. The primary goal of our mapping algorithm is to minimize the depth of the mapped circuit. Meanwhile, we have successfully reduced the area of the mapped circuits by applying several heuristic techniques, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA-packing. We compare our PLAmap with a recently-published algorithm TEMPLA [1] and a commercial tool, Altera's MAX+PLUS II [16]. Experimental results on various MCNC benchmarks show that overall TEMPLA uses 8 to 11% less area at the cost of 96 to 106% more mapping depth, and MAX+PLUS II uses 12% less area but 58% more delay compared with our mapper.

关键词： programmable logic controllers

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Reprogrammable network packet processing on the field programmable Port Extender (FPX) 01

Reprogrammable network packet processing on the Field Progra...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lockwood, J.W. Naufel, N. Turner, J.S. Taylor, D.E. Department of Computer Science Applied Research Lab. Washington University 1 Brookings Drive Saint Louis MO 63130 United States

ISBN: (纸本)9781581133417

A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the field programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two field programmable gate arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules. Core functionality of the FPX is implemented on an FPGA called the Networking Interface Device (NID). The NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second FPGA called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the FPGA. Through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. The platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. The modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.

关键词： Packet networks

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The case for registered routing switches in field programmable gate arrays 01

The case for registered routing switches in field programmab...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Singh, D.P. Brown, S.D. Department of Electrical Engineering University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581133417

FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit. In this paper we investigate architectural features that could allow us to automatically pipeline the delay associated with long routes without an excessive area penalty. The goal is to reschedule circuit operations in such a way that a signal may use multiple clock cycles to traverse a long route, rather than requiring a single long clock period. This rescheduling would not effect the timing of the visible outputs (no latency is added to the overall system). Specifically, we analyze the effects of adding a small number of registered routing switches to an FPGA architecture with segmented routing resources. A parameterized FPGA architecture is studied where the percentage of registered routing switches is varied and the speed improvement and area penalty is evaluated. Novel algorithms are presented that allow a circuit to best utilize an architecture with a given percentage of registered switches. We believe that this is the first study that attempts to evauate the tradeoffs associated with switches required in FPGA architectures. Our experiments indicate that the architectural features introduced can produce significant speedup for high speed circuits without excessive area costs. We believe that these techniques will become increasingly important in the future as deep sub-micron process technologies shrink, and wire delays become even more significant.

关键词： field programmable gate arrays

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Timing-driven placement for hierarchical programmable logic devices 01

Timing-driven placement for hierarchical programmable logic ...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Hutton, M. Adibsamii, K. Leaver, A. Altera Corporation 101 Innovation Drive San Jose CA 95134 United States

ISBN: (纸本)9781581133417

In this paper we discuss new techniques for timing-driven placement and adaptive delay computation for hierarchical PLD architectures. Our algorithm follows the natural recursive k-way partitioning-based approach to placement on such devices. Our contributions include a specification of the overall TDC (timing-driven compilation) algorithm, an analysis of heuristics such as a variant of multi-start partitioning, a new method for adaptive delay computation, and a discussion of the structure of critical paths and sub-graphs on modern PLD designs. This algorithm has been implemented in a production quality commercial tool, and we report on the results with and without the implementation of the new techniques. The basic result is a substantial 38.5% average (36.3% median) improvement in register-to-register performance across a range of real designs in modern density ranges, at a cost of approximately 3.65X average (2.88X median) place-and-route CPU time. (These improvements and costs are relative to the same tool prior to the efforts described in this paper.) A partial implementation of the new algorithm shows approximately half the performance gain, with approximately half the compile time cost.

关键词： programmable logic controllers

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Detailed routing architectures for embedded programmable logic IP cores 01

Detailed routing architectures for embedded programmable log...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Hallschmid, P. Wilton, S.J.E. Department of Electrical Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581133417

As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Compared to a simple extension of an existing switch block, our new architecture leads to an 8.7% improvement in density with little effect on speed. Finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small;for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 1.1%.

关键词： Application specific integrated circuits

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