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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"
629 条 记 录,以下是481-490 订阅
排序:
Interconnect pipelining in a throughput-intensive FPGA architecture  01
Interconnect pipelining in a throughput-intensive FPGA archi...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Singh, A. Mukherjee, A. Marek-Sadowska, M. Department of Electrical Engineering University of California Santa Barbara CA 93106 United States
Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, circuits inherently utilize lat... 详细信息
来源: 评论
An FPGA-based video compressor for H.263 compatible bit streams  01
An FPGA-based video compressor for H.263 compatible bit stre...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Lienhart, G. Männer, R. Lay, R. Noffz, K.H. Dept. for Computer Science V University of Mannheim D-68131 Mannheim Germany
This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA and is embedded in a PCI plug-in car... 详细信息
来源: 评论
LRoute: A delay minimal router for hierarchical CPLDs  01
LRoute: A delay minimal router for hierarchical CPLDs
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Lee, K.K. Wong, M.D.F. Synopsys Inc. 700 E. Middlefield Rd Mountain View CA 94043 United States
This paper describes LRoute, a novel router for the popular and scalable hierarchical Complex programmable Logic Devoices (CPLDs). CPLD routing has constraints om routing topologies due to architectural limitations an... 详细信息
来源: 评论
Configuration compression for FPGA-based embedded systems  01
Configuration compression for FPGA-based embedded systems
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Dandalis, A. Prasanna, V.K. Electrical Engineering - Systems University of Southern California 3740 McClintock Avenue Los Angeles CA 90089-2562 United States
FPGAs are a promising technology for developing high-performance embedded systems. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration bi... 详细信息
来源: 评论
Matching and searching analysis for parallel hardware implementation on FPGAs  01
Matching and searching analysis for parallel hardware implem...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Moisset, P. Diniz, P. Park, J. University of Southern California Information Sciences Institute 4676 Admiralty Way Marina del Rey CA 90292 United States
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a simple search/matching predicate. The... 详细信息
来源: 评论
Performance-driven mapping for CPLD architectures  01
Performance-driven mapping for CPLD architectures
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Chen, D. Cong, J. Ercegovac, M.D. Huang, Z. Department of Computer Science University of California Los Angeles CA 90095 United States
In this paper we present a performance-driven mapping algorithm, PLAmap, for CPLD architectures which consist of a large number of PLA-style logic cells. The primary goal of our mapping algorithm is to minimize the de... 详细信息
来源: 评论
Reprogrammable network packet processing on the field programmable Port Extender (FPX)  01
Reprogrammable network packet processing on the Field Progra...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Lockwood, J.W. Naufel, N. Turner, J.S. Taylor, D.E. Department of Computer Science Applied Research Lab. Washington University 1 Brookings Drive Saint Louis MO 63130 United States
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the field programmable Port Extender (FPX), enables packet processing fu... 详细信息
来源: 评论
The case for registered routing switches in field programmable gate arrays  01
The case for registered routing switches in field programmab...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Singh, D.P. Brown, S.D. Department of Electrical Engineering University of Toronto Toronto Ont. Canada
FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, ... 详细信息
来源: 评论
Timing-driven placement for hierarchical programmable logic devices  01
Timing-driven placement for hierarchical programmable logic ...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Hutton, M. Adibsamii, K. Leaver, A. Altera Corporation 101 Innovation Drive San Jose CA 95134 United States
In this paper we discuss new techniques for timing-driven placement and adaptive delay computation for hierarchical PLD architectures. Our algorithm follows the natural recursive k-way partitioning-based approach to p... 详细信息
来源: 评论
Detailed routing architectures for embedded programmable logic IP cores  01
Detailed routing architectures for embedded programmable log...
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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)
作者: Hallschmid, P. Wilton, S.J.E. Department of Electrical Engineering University of British Columbia Vancouver BC Canada
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. T... 详细信息
来源: 评论