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Transistor-Level Monolithic 3D Standard Cell Layout Optimization for Full-Chip Static Power Integrity 22

Transistor-Level Monolithic 3D Standard Cell Layout Optimiza...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ku, Bon Woong Song, Taigon Nieuwoudt, Arthur Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Synopsys Inc Mountain View CA USA

ISBN: (纸本)9781509060238

Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs 22

Frequency and Time Domain Analysis of Power Delivery Network...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Das, Shidhartha Sinha, Saurabh Cline, Brian Yeric, Greg Lim, Sung Kyu Georgia Inst Teehnol Sch ECE Atlanta GA 30332 USA ARM Ltd Cambridge England ARM Inc Austin TX USA

ISBN: (纸本)9781509060238

As 2D scaling reaches its limit, monolithic 3D IC (M3D) is a leading contender to continue equivalent scaling. AIthough M3D shows power and performance benefits over 2D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power-supply integrity. In addition, we present frequency- and time-domain analysis of the M3D PDN. We show that the additional resistance in the M3D PDN, while being worse for resistive drops, improves resiliency against current noise showing 35.9% peak impedance reduction during worst-case resonant oscillations.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Full Chip Power Benefits with Negative Capacitance FETs 22

Full Chip Power Benefits with Negative Capacitance FETs

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Samal, Sandeep K. Khandelwal, Sourabh Khan, Asif I. Salahuddin, Sayeef Hu, Chenming Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Macquarie Univ Dept Engn Sydney NSW Australia Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA

ISBN: (纸本)9781509060238

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercialgrade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4X (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition 22

Monolithic 3D IC Designs for Low-Power Deep Neural Networks ...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Kadetotad, Deepak Cao, Yu Seo, Jae-sun Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Arizona State Univ Sch ECEE Tempe AZ USA

ISBN: (纸本)9781509060238

In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Sequencing Run-Time Reconfigured Hardware with Software

Sequencing Run-Time Reconfigured Hardware with Software

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： M.J. Wirthlin B.L. Hutchings Department of Electrical and Computer Engineering Brigham Young University Provo UT USA

Run-Time Reconfigured systems offer additional hardware resources to systems based on reconfigurable FPGAs. These systems, however, are often difficult to build and must tolerate substantial reconfiguration times. A processor based architecture has been built to simplify the development of these systems by providing programmable control of hardware sequencing while retaining the performance of hardware. Configuration overhead of this system is reduced by "caching" hardware on the reconfigurable resource. An image processing application was developed on this system to demonstrate both the performance improvements of custom hardware and the ease of software development.

关键词： Runtime Hardware field programmable gate arrays

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Hybrid FPGA Architecture

Hybrid FPGA Architecture

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： A. Kaviani S. Brown Department of Electrical and Computer Engineering University of Toronto Canada

This paper proposes a new field-programmable architecture that is a combination of two existing technologies: field programmable gate arrays (FPGAs) based on LookUp Tables (LUTs), and Complex programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The proposed Hybrid FPGA is evaluated by manually technology mapping a set of circuits into the new architecture and estimating the total chip area needed for each circuit, compared to the area that would be required if only LUTs were available. Preliminary results indicate that compared to LUT-based FPGAs the Hybrid offers savings of more than a factor of two in terms of chip area.

关键词： field programmable gate arrays Table lookup Logic arrays programmable logic arrays Computer aided manufacturing CADCAM Logic circuits Semiconductor device measurement Computer architecture Random access memory

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A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic 22

A Carbon Nanotube Transistor based RISC-V Processor using Pa...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Amarnath, Aporva Feng, Siying Pal, Subhankar Ajayi, Tutu Rovinski, Austin Dreslinski, Ronald G. Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781509060238

With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over siliconbased counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energyefficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9. EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5x as well as reduce area by 17% over 16 nm silicon CMOS.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Method for Generation Random Circuits and Its Application to Routability Measurement

A Method for Generation Random Circuits and Its Application ...

引用

proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： J. Darnauer W.W. Dai Computer Engineering University of California Santa Cruz Santa Cruz CA USA

FPLD architectures are often designed based on the results of experiments with "typical" benchmark circuits. For very large FPLDs, it may be difficult to obtain enough benchmark circuits to accurately evaluate an architecture. In this paper, we present a method for generating large random circuits with a fixed number of inputs, outputs, blocks, pins per cell, and approximate rent exponent. The circuits generated are used to evaluate several routability measures. We find that routability is best predicted by estimating the total wirelength in the circuit, not the mean wirelength times pins per cell.

关键词： Circuits field programmable gate arrays

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Diagnosing programmable Interconnect Systems for FPGAs

Diagnosing Programmable Interconnect Systems for FPGAs

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： F. Lombardi D. Ashen Xiaotao Chen Wei Kang Huang Department of Computer Science Texas A and M University College Station TX USA Department of Electronic Engineering Fudan University Shanghai China

This paper deals with the diagnosis of field programmable interconnect systems (FPIS) in which nets are connected through programmable switches arranged in grids. A hierarchical approach to diagnosis is proposed. The conditions by which such process yields full diagnosis and the characteristics of the programming sequence, are fully proved. For a FPIS consisting of a k x k grid array, the number of tests is given by 4 + 4kn^2, while the number of programming steps is 4nk + 1, where n is the dimension of a grid. The application of this technique to commercially available FPIS in FPGAs, is discussed.

关键词： field programmable gate arrays

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Entropy, Counting, and programmable Interconnect

Entropy, Counting, and Programmable Interconnect

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： A. DeHon Artificial Intelligence Laboratory MIT Cambridge MA USA

Conventional reconfigurable components have substantially more interconnect configuration bits than they strictly need. Using counting arguments we can establish loose bounds on the number of programmable bits actually required to describe an interconnect. We apply these bounds in crude form to some existing devices, demonstrating the large redundancy in their programmable bit streams. In this process we review and demonstrate basic counting techniques for identifying the information required to specify an interconnect. We examine several common interconnect building blocks and look at how efficiently they use the information present in their programming bits. We also discuss the impact of this redundancy on important device aspects such as area, routing, and reconfiguration time.

关键词： Entropy Switches Wire Bandwidth field programmable gate arrays Random access memory Table lookup Artificial intelligence Laboratories Routing

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