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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC 29

Vicilogic 2.0: Online Learning and Prototyping of Digital Sy...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Morgan, Fearghal O'loughlin, Declan Audiger, Jeremy Boyer, Yohan Timlin-Canning, Niall Kepa, Krzysztof Cawley, Seamus Gallivan, Ian Bako, László Callaly, Frank National University of Ireland Galway Ireland Sapientia Hungarian University of Transylvania Romania

ISBN: (纸本)9781538675571

This paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. The viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. The platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. This enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. The prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. The builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. The paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE). © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Amplifying embedded system efficiency via automatic instruction fusion on a post-manufacturing reconfigurable architecture platform

Amplifying embedded system efficiency via automatic instruct...

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9th international symposium on Quality Electronic Design

作者： Cheng, Allen C. Univ Pittsburgh Adv Comp Technol Lab Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9780769531175

Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability;while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM;FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible Versatile Processing Unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.

关键词： field programmable gate arrays (FPGA)

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A 100 MHz PLL implemented on a 100K gate programmable logic device (abstract) 98

A 100 MHz PLL implemented on a 100K gate programmable logic ...

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proceedings of the 1998 acm/sigda sixth international symposium on field programmable gate arrays

作者： David Jefferson Srinivas Reddy Christopher Lane Ninh Ngo Wanli Chang Manuel Mijia Ketan Zaveri Cameron McClintock Richard Cliff

No abstract available.

ISBN: (纸本)9780897919784

No abstract available.

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Dynamically programmable cache evaluation and virtualization (abstract only) 99

Dynamically programmable cache evaluation and virtualization...

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proceedings of the 1999 acm/sigda seventh international symposium on field programmable gate arrays

作者： Mouna Nakkar David G. Bentlage John Harding David Schwartz Paul Franzon Thomas Conte North Carolina State University

No abstract available.

ISBN: (纸本)9781581130881

No abstract available.

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Evaluation of FPGA Resources for Built-In Self-Test of programmable Logic Blocks

Evaluation of FPGA Resources for Built-In Self-Test of Progr...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： C. Stroud Ping Chen S. Konala M. Abramovici Department of Electrical Engineering University of Kentucky USA AT and T Bell Laboratories Inc. Murray Hill NJ USA

We present a new approach for FPGA testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without area or performance penalties to the system function implemented by the FPGA, since the FPGA is reconfigured for normal system operation. An analysis of Look-Up Table (LUT) based FGPA architectures yields a general expression for the number of test sessions and establishes the bounds on FPGA logic resources required to minimize the number of BIST configurations required to completely test all of the programmable logic blocks of an FPGA.

关键词： field programmable gate arrays Built-in self-test programmable logic arrays programmable logic devices Logic testing Circuit testing System testing Logic devices Test pattern generators Pattern analysis

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Flexible FPGA Architecture realized of General Purpose SOG

Flexible FPGA Architecture realized of General Purpose SOG

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： K. Azegami S. Kashiwakura K. Yamashita Fujitsu Laboratories Limited Kawasaki Japan

In this paper, we describe an FPGA of high realization method flexibility, using general purpose SOG (sea of gates) gate array. Realization method flexibility means that we can realize the architecture by any method of realization, i.e. gate arrays and full customs. FPGAs determine their functions from their programmed internal state circuit. For example, SRAM program FPGAs do so by setting values to SRAMS. Our FPGA also uses SRAM program memory, but not limited. We will show one example of realization using general purpose SOG gate arrays. Our test SOG FPGA has a capacity of 6.5Kgate on a 14mm x 14mm die, with less than 2ns propagation delay between local logic cells.

关键词： field programmable gate arrays

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Computing the Discrete Fourier Transform on FPGA Based Systolic arrays

Computing the Discrete Fourier Transform on FPGA Based Systo...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： C. Dick School of Electronic Engineering La Trobe University Melbourne Australia

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using virtual computers based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that provides the system designer with a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution time are calculated.

关键词： Discrete Fourier transforms field programmable gate arrays Systolic arrays Logic arrays Reconfigurable logic Hardware Logic circuits Flexible printed circuits Computer architecture Arithmetic

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An Energy-efficient and High-throughput Bitwise CNN on Sneak-path-free Digital ReRAM Crossbar 22

An Energy-efficient and High-throughput Bitwise CNN on Sneak...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ni, Leibin Liu, Zichuan Song, Wenhao Yang, J. Joshua Yu, Hao Wang, Kanwen Wang, Yuangang Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA Huawei Technol Co Ltd Data Ctr Technol Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781509060238

Convolutional neural network (CNN) based machine learning requires a highly parallel as weIl as low power consumption (including leakage power) hardware accelerator. In this paper, we will present a digital ReRAM cross bar based CNN accelerator that can achieve significantly higher throughput and lower power consumption than state-of-arts. The CNN is trained with binary constraints on both weights and activations such that all operations become bitwise. With further use of I-bit comparator, the bitwise CNN model can be naturally realized on a digital ReRAM-crossbar device. A novel sneak-path-free ReRAM-crossbar is further utilized for large-scale realization. Simulation experiments show that the bitwise CNN accelerator on the digital ReRAM crossbar achieves 98.3% and 91. 4% accuracy on MNIST and CIFAR-IO benchmarks, respectively. Moreover, it has a peak throughput of 792GOPS at the power consumption of 6.3mW, which is 18.86 times higher throughput and 44.1 times lower power than CMOS CNN (non-binary) accelerators.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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AXSERBUS: A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensing 22

AXSERBUS: A Quality-Configurable Approximate Serial Bus for ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Kim, Younghyun Behroozi, Setareh Raghunathan, Vijay Raghunathan, Anand Univ Wisconsin Dept Elect & Comp Engn Maison WI 53706 USA Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Mobile, wearable, and implantable devices integrate an increasing number and variety of sensors such as microphones, image sensors, and accelerometers. These devices spend substantial amounts of time reading the sensors within them, thereby incurring significant energy dissipation over off-chip serial interconnects. This paper proposes AXSERBUS, a quality-configurable approximate serial bus that exploits the locality of sensory data and the error resiliency of sensing applications to reduce energy dissipation. AXSERBUS significantly reduces signal transitions by encoding the differentials of sensory data in three encoding modes, depending on the magnitude of the differentials: very small differentials are zeroed out, incurring no energy dissipation;intermediate differentials are encoded using special low-transition count patterns;and for high differentials, the absolute value (not the differential) of the data is transmitted. Compared to previous schemes, the proposed multi-level encoding results in more data being encoded as low-energy patterns. In addition, in the intermediate differential encoding mode, the differentials are encoded in an approximate manner, and the approximation bounds are proportional to the magnitude of the differentials. Since small differentials are more frequent than large differentials in sensory data, the proposed encoding scheme also minimizes quality degradation. We demonstrate that AXSERBUS achieves improved energy vs. quality tradeoffs compared to previous schemes. In the context of an optical character recognition (OCR) application, AXSERBUS achieves 79.4% reduction in dynamic power dissipation, while maintaining accuracy above 95%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Design and Implementation of a field programmable Analogue Array

Design and Implementation of a Field Programmable Analogue A...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： A. Bratt I. Macbeth Gadbrook Business Centre Pilkington Micro-Electronics Limited Northwich Cheshire UK

A field programmable Analogue Array (FPAA) is presented based on switched capacitor technology. The chip allows true array programming of undedicated analogue cells. There is provision for internal signal-conditional switching as part of the normal function of the array. With the presented chip it is possible to implement a very wide range of analogue signal processing functions such as data conversion, linear signal processing and non-linear functions. These functional configurations can be reconfigured and parameterised on the fly during concurrent signal processing. Very rapid prototyping of switched capacitor circuits is facilitated. The field programmable nature of the chip allows several markets/customers to be targeted simultaneously with obvious benefits in terms of both volume of sales and reduced time to market.

关键词： field programmable analog arrays Array signal processing Switched capacitor circuits Switches Integrated circuit interconnections Signal design Transfer functions Data conversion Prototypes Marketing and sales

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