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Amplifying embedded system efficiency via automatic instruction fusion on a post-manufacturing reconfigurable architecture platform

Amplifying embedded system efficiency via automatic instruct...

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9th international symposium on Quality Electronic Design

作者： Cheng, Allen C. Univ Pittsburgh Adv Comp Technol Lab Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9780769531175

Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability;while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM;FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible Versatile Processing Unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.

关键词： field programmable gate arrays (FPGA)

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Plasma: An FPGA for Million gate Systems

Plasma: An FPGA for Million Gate Systems

引用

proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： R. Amerson R. Carter W. Culbertson P. Kuekes G. Snider L. Albertson Hewlett Packard Laboratories Palo Alto CA USA Hewlett-Packard California Design Center Palo Alto CA USA

Prototypes are invaluable for studying special purpose parallel architectures and custom computing. This paper describes a new FPGA, called Plasma- the heart of a configurable custom computing engine (Teramac) that can execute synchronous logic designs up to one million gates at rates up to one megahertz. Plasma FPGA's using 0.8 micron CMOS are packaged in large multichip modules (MCMs). A large custom circuit may be mapped onto the hardware in approximately two hours, without user intervention. Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

关键词： field programmable gate arrays Plasma applications Hardware Prototypes Parallel architectures Concurrent computing Heart Engines Logic design Packaging

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Computing the Discrete Fourier Transform on FPGA Based Systolic arrays

Computing the Discrete Fourier Transform on FPGA Based Systo...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： C. Dick School of Electronic Engineering La Trobe University Melbourne Australia

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using virtual computers based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that provides the system designer with a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution time are calculated.

关键词： Discrete Fourier transforms field programmable gate arrays Systolic arrays Logic arrays Reconfigurable logic Hardware Logic circuits Flexible printed circuits Computer architecture Arithmetic

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SceneMan: Bridging Mobile Apps with System Energy Manager via Scenario Notification 22

SceneMan: Bridging Mobile Apps with System Energy Manager vi...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Li, Li Wang, Jun Wang, Xiaorui Ye, Handong Hu, Ziang Ohio State Univ Columbus OH 43210 USA Huawei US R&D Santa Clara CA USA

ISBN: (纸本)9781509060238

Power management on current mobile devices relies on OS modules known as DVFS governors. However, existing governors determine system configuration only based on low-level information such as CPU load without any input about application-level behaviors. In particular, there exists no communication from mobile apps to energy managers. We find that information about app usage scenarios (e.g., gaming, video chatting) can usually help energy manager perform a better job and achieve more energy savings. Although app-level energy optimizations have been proposed, they generally focus on single usage scenarios and do not address optimization across multiple scenarios. In this paper, we propose SceneMan, an energy optimization framework for mobile apps based on usage scenario notification. SceneMan has three components: an API, a scenario notifier, and an energy manager. The key idea is to make energy managers aware of app-level scenarios. At runtime, apps notify the energy manager about their usage scenarios with provided APIs used by developers. The energy manager then takes appropriate actions to minimize energy consumption of the running scenario while meeting performance requirements. Energy optimization across scenarios can thus be easily achieved. The framework requires little extra programming effort and can help apps achieve better energy efficiency in a transparent way. We implement our system on a Nexus 6 smartphone and test it with 13 real-world apps under 2 usage scenarios, namely, gaming and video chatting. We achieve up to 33.2% energy savings with a worst-case performance loss of 5.1%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Online Tuning of Dynamic Power Management for Efficient Execution of Interactive Workloads 22

Online Tuning of Dynamic Power Management for Efficient Exec...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Bantock, James R. B. Tenentes, Vasileios Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Dept Elect & Comp Sci Southampton Hants England

ISBN: (纸本)9781509060238

Modern mobile devices contain powerful MultiProcessor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Power Optimizations in MTJ-based Neural Networks through Stochastic Computing 22

Power Optimizations in MTJ-based Neural Networks through Sto...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mondal, Ankit Srivastava, Ankur Univ Maryland Dept Elect & Comp Engn College Pk MD 20783 USA

ISBN: (纸本)9781509060238

Artificial Neural Networks (ANNs) have found widespread applications in tasks such as pattern recognition and image classification. However, hardware implementations of ANNs using conventional binary arithmetic units are computationally expensive, energy-intensive and have large area overheads. Stochastic Computing (SC) is an emerging paradigm which replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. Spintronic devices, such as Magnetic Tunnel Junctions (MTJs), are capable of replacing CMOS in memory and logic circuits. In this work, we propose an energy-efficient use of MTJs, which exhibit probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, error resilient target applications of NNs allow us to introduce Approximate Computing, a framework wherein accuracy of computations is traded-off for substantial reductions in power consumption. We propose approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of our MTJ-SNG, to achieve energy-efficiency. We design an algorithm that can perform such approximations within a given error tolerance in a single-layer NN in an optimal way owing to the convexity of the problem formulation. We then use this algorithm and develop a heuristic approach for approximating multi-layer NNs. To give a perspective of the effectiveness of our approach, a 43% reduction in power consumption was obtained with less than 1% accuracy loss on a standard classification problem, with 26% being brought about by the proposed algorithm.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (FPGA)

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The EPAC architecture: an expert cell approach to field programmable analog devices 96

The EPAC architecture: an expert cell approach to field prog...

引用

proceedings of the 1996 acm fourth international symposium on field-programmable gate arrays

作者： Hans W. Klein IMP Inc. San Jose CA

No abstract available.

ISBN: (纸本)9780897917735

No abstract available.

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A fully onchip binarized convolutional neural network FPGA impelmentation with accurate inference 18

A fully onchip binarized convolutional neural network FPGA i...

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23rd IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2018

作者： Yang, Li He, Zhezhi Fan, Deliang Department of Electrical and Computer Engineering OrlandoFL United States

ISBN: (纸本)9781450357043

Deep convolutional neural network has taken an important role in machine learning algorithm which has been widely used in computer vision tasks. However, its enormous model size and massive computation cost have became the main obstacle for deployment of such powerful algorithm in low power and resource limited embedded system, such as FPGA. Recent works have shown the binarized neural networks (BNN), utilizing binarized (i.e. +1 and -1) convolution kernel and binary activation function, can significantly reduce the model size and computation complexity, which paves a new road for energy-efficient FPGA implementation. In this work, we first propose a new BNN algorithm, called Parallel-Convolution BNN (i.e. PC-BNN), which replaces the original binary convolution layer in conventional BNN with two parallel binary convolution layers. PC-BNN achieves ∼86% on CIFAR-10 dataset with only 2.3Mb parameter size. We then deploy our proposed PC-BNN into the Xilinx PYNQ Z1 FPGA board with only 4.9Mb on-chip RAM. Since the ultra-small network parameter, it is feasible to store the whole network parameter into on-chip RAM, which could greatly reduce the energy and delay overhead to load network parameter from off-chip memory. Meanwhile, a new data streaming pipeline architecture is proposed in PC-BNN FPGA implementation to further improve throughput. The experiment results show that our PCBNN based FPGA implementation achieves 930 frames per second, 387.5 FPS/Watt and 396×10-4 FPS/LUT, which are among the best throughput and energy efficiency compared to most recent works. © 2018 Association for Computing Machinery.

关键词： field programmable gate arrays (FPGA)

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Study on the application of FPGA in transformer terminal unit 4

Study on the application of FPGA in transformer terminal uni...

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4th international symposium on Power Electronics and Control Engineering, ISPECE 2021

作者： Zhong, W. Wang, C. Jiangsu Frontier Electric Technology Co. Ltd Nanjing211103 China

ISBN: (数字)9781510650374

ISBN: (纸本)9781510650367

This paper introduces a transformer terminal unit (TTU) signal acquisition system based on field programmable gate array (FPGA). The TTU signal acquisition system is realized based on demo board of FPGA (model EP4CE10F17C8), and the corresponding chips and schematic diagrams are also introduced. On the basis of the hardware module, the signal acquisition and display program is written in Verilog HDL language. A signal generator is used to generate voltage signals with different waveforms to simulate the signals acquired by the TTU. Based on the signal acquisition system, these voltage signals are acquired and displayed. The harmonics of the acquired signals are analyzed by fast Fourier transform (FFT). The results of the developed system are consistent with those by the oscilloscope. This work verifies the applicability of FPGA in TTU, and also provides a reference for the implementation of high-performance TTU. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： field programmable gate arrays (FPGA)

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