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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"
629 条 记 录,以下是531-540 订阅
排序:
Exploiting FPGA-features during the emulation of a fast reactive embedded system
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 235-242页
作者: Weiss, Karlheinz Steckstor, Thorsten Koch, Gernot Rasenstiel, Wolfgang Univ of Tuebingen Tuebingen Germany
This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220 μs. We show that for such fast reactive systems, the software overhead of a Real Time Operating ... 详细信息
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Innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 17-26页
作者: Agrawal, Om Chang, Herman Sharpe-Geisler, Brad Schmitz, Nick Nguyen, Bai Wong, Jack Tran, Giap Fontana, Fabiano Harding, Bill Vantis Corp Sunnyvale CA United States
This paper describes the Vantis VF1 FPGA architecture, an innovative architecture based on 0.25 u (drawn) (0.18 u Leff)/4-metal technology. It was designed from scratch for high performance, routability and ease-of-us... 详细信息
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Methodology for fast FPGA floorplanning
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 47-56页
作者: Emmert, John M. Bhatia, Dinesh Univ of Cincinnati Cincinnati United States
Floorplanning is an important problem in FPGA circuit mapping. As FPGA capacity grows, new innovative approaches will be required for efficiently mapping circuits to FPGAs. In this paper we present a macro based floor... 详细信息
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HSRA: High-speed, hierarchical synchronous reconfigurable array
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 125-134页
作者: Tsu, William Macy, Kip Joshi, Atul Huang, Randy Walker, Norman Tung, Tony Rowhani, Omid George, Varghese Wawrzynek, John DeHon, Andre Univ of California at Berkeley Berkeley United States
There is no inherent characteristic forcing field programmable gate Array (FPGA) or Reconfigurable Computing (RC) Array cycle times to be greater than processors in the same process. Modern FPGAs seldom achieve applic... 详细信息
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Procedural texture mapping on FPGAs
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 112-120页
作者: Ye, Andy G. Lewis, David M. Univ of Toronto Toronto Ont Canada
Procedural textures can be effectively used to enhance the visual realism of computer rendered images. Procedural textures can provide higher realism for 3-D objects than traditional hardware texture mapping methods w... 详细信息
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Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 37-46页
作者: Marquardt, Alexander Betz, Vaughn Rose, Jonathan Univ of Toronto Toronto Ont Canada
In this paper, we investigate the speed and area-efficiency of FPGAs employing `logic clusters' containing multiple LUTs and registers as their logic block. We introduce a new, timing-driven tool (T-VPack) to `pac... 详细信息
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Memory interfacing and instruction specification for reconfigurable processors
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 145-154页
作者: Jacob, Jeffrey A. Chow, Paul Univ of Toronto Toronto Ont Canada
As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory. This paper describes the architecture of a custom computing machine that ... 详细信息
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FPGA routing architecture: Segmentation and buffering to optimize speed and density
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 59-68页
作者: Betz, Vaughn Rose, Jonathan Univ of Toronto Toronto Canada
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transistor and tri-state buffer routing switch... 详细信息
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Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 29-35页
作者: Cong, Jason Wu, Chang Ding, Yuzheng Univ of California Los Angeles United States
Cut enumeration is a common approach used in a number of FPGA synthesis and mapping algorithms for consideration of various possible LUT implementations at each node in a circuit. Such an approach is very general and ... 详细信息
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Multi-terminal net routing for partial crossbar-based multi-FPGA systems
ACM/SIGDA International Symposium on Field Programmable Gate...
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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 176-184页
作者: Ejnioui, Abdel Ranganathan, N. Univ of South Florida Tampa FL United States
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multi-termi... 详细信息
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