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Power Optimizations in MTJ-based Neural Networks through Stochastic Computing 22

Power Optimizations in MTJ-based Neural Networks through Sto...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mondal, Ankit Srivastava, Ankur Univ Maryland Dept Elect & Comp Engn College Pk MD 20783 USA

ISBN: (纸本)9781509060238

Artificial Neural Networks (ANNs) have found widespread applications in tasks such as pattern recognition and image classification. However, hardware implementations of ANNs using conventional binary arithmetic units are computationally expensive, energy-intensive and have large area overheads. Stochastic Computing (SC) is an emerging paradigm which replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. Spintronic devices, such as Magnetic Tunnel Junctions (MTJs), are capable of replacing CMOS in memory and logic circuits. In this work, we propose an energy-efficient use of MTJs, which exhibit probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, error resilient target applications of NNs allow us to introduce Approximate Computing, a framework wherein accuracy of computations is traded-off for substantial reductions in power consumption. We propose approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of our MTJ-SNG, to achieve energy-efficiency. We design an algorithm that can perform such approximations within a given error tolerance in a single-layer NN in an optimal way owing to the convexity of the problem formulation. We then use this algorithm and develop a heuristic approach for approximating multi-layer NNs. To give a perspective of the effectiveness of our approach, a 43% reduction in power consumption was obtained with less than 1% accuracy loss on a standard classification problem, with 26% being brought about by the proposed algorithm.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Is marriage in the cards for programmable logic, microprocessors and ASICs? 01

Is marriage in the cards for programmable logic, microproces...

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proceedings of the 2001 acm/sigda ninth international symposium on field programmable gate arrays

作者： John East Tim Garverick Scott Hauck Tavana Tavana Steve Trimberger Ronnie Vasishta Sinan Kaptanoglu Actel Adaptive Silicon University of Washington Triscend Xilinx LSI Logic

No abstract available.

ISBN: (纸本)9781581133417

No abstract available.

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A Power-Efficient and Non-volatile programmable Logic Array Based on Phase Change Memory

A Power-Efficient and Non-volatile Programmable Logic Array ...

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international Workshop on Information Data Storage / 10th international symposium on Optical Storage

作者： Du, Yuan Ye, Yong Kang, Yong Xia, Yangyang Song, Zhitang Chen, Bomy Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol State Key Lab Funct Mat Informat Shanghai 200050 Peoples R China Univ Chinese Acad Sci Beijing 10080 Peoples R China Shanghai Xinchu Integrated Circuit Incorp Shanghai 200122 Peoples R China

ISBN: (纸本)9781510600591

Recently, numerous efforts have been made on NVM-based field programmable gate arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can't be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of programmable Element is OFF.

关键词： PLA SRAM PCM low-power reconfigurable logic

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A fully onchip binarized convolutional neural network FPGA impelmentation with accurate inference 18

A fully onchip binarized convolutional neural network FPGA i...

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23rd IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2018

作者： Yang, Li He, Zhezhi Fan, Deliang Department of Electrical and Computer Engineering OrlandoFL United States

ISBN: (纸本)9781450357043

Deep convolutional neural network has taken an important role in machine learning algorithm which has been widely used in computer vision tasks. However, its enormous model size and massive computation cost have became the main obstacle for deployment of such powerful algorithm in low power and resource limited embedded system, such as FPGA. Recent works have shown the binarized neural networks (BNN), utilizing binarized (i.e. +1 and -1) convolution kernel and binary activation function, can significantly reduce the model size and computation complexity, which paves a new road for energy-efficient FPGA implementation. In this work, we first propose a new BNN algorithm, called Parallel-Convolution BNN (i.e. PC-BNN), which replaces the original binary convolution layer in conventional BNN with two parallel binary convolution layers. PC-BNN achieves ∼86% on CIFAR-10 dataset with only 2.3Mb parameter size. We then deploy our proposed PC-BNN into the Xilinx PYNQ Z1 FPGA board with only 4.9Mb on-chip RAM. Since the ultra-small network parameter, it is feasible to store the whole network parameter into on-chip RAM, which could greatly reduce the energy and delay overhead to load network parameter from off-chip memory. Meanwhile, a new data streaming pipeline architecture is proposed in PC-BNN FPGA implementation to further improve throughput. The experiment results show that our PCBNN based FPGA implementation achieves 930 frames per second, 387.5 FPS/Watt and 396×10-4 FPS/LUT, which are among the best throughput and energy efficiency compared to most recent works. © 2018 Association for Computing Machinery.

关键词： field programmable gate arrays (FPGA)

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Plasma: An FPGA for Million gate Systems

Plasma: An FPGA for Million Gate Systems

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： R. Amerson R. Carter W. Culbertson P. Kuekes G. Snider L. Albertson Hewlett Packard Laboratories Palo Alto CA USA Hewlett-Packard California Design Center Palo Alto CA USA

Prototypes are invaluable for studying special purpose parallel architectures and custom computing. This paper describes a new FPGA, called Plasma- the heart of a configurable custom computing engine (Teramac) that can execute synchronous logic designs up to one million gates at rates up to one megahertz. Plasma FPGA's using 0.8 micron CMOS are packaged in large multichip modules (MCMs). A large custom circuit may be mapped onto the hardware in approximately two hours, without user intervention. Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

关键词： field programmable gate arrays Plasma applications Hardware Prototypes Parallel architectures Concurrent computing Heart Engines Logic design Packaging

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Study on the application of FPGA in transformer terminal unit 4

Study on the application of FPGA in transformer terminal uni...

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4th international symposium on Power Electronics and Control Engineering, ISPECE 2021

作者： Zhong, W. Wang, C. Jiangsu Frontier Electric Technology Co. Ltd Nanjing211103 China

ISBN: (数字)9781510650374

ISBN: (纸本)9781510650367

This paper introduces a transformer terminal unit (TTU) signal acquisition system based on field programmable gate array (FPGA). The TTU signal acquisition system is realized based on demo board of FPGA (model EP4CE10F17C8), and the corresponding chips and schematic diagrams are also introduced. On the basis of the hardware module, the signal acquisition and display program is written in Verilog HDL language. A signal generator is used to generate voltage signals with different waveforms to simulate the signals acquired by the TTU. Based on the signal acquisition system, these voltage signals are acquired and displayed. The harmonics of the acquired signals are analyzed by fast Fourier transform (FFT). The results of the developed system are consistent with those by the oscilloscope. This work verifies the applicability of FPGA in TTU, and also provides a reference for the implementation of high-performance TTU. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： field programmable gate arrays (FPGA)

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Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance

Technology Mapping of Sequential Circuits for LUT-Based FPGA...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： Peichen Pan C.L. Liu Department of Electrical & Computer Engineering Clarkson University Potsdam NY USA Department of Computer Science University of Illinois Urbana-Champaign IL USA

In this paper, we study the technology mapping problem for sequentail circuits for LUT-based FPGAs. The conventional approach for this problem is based on a technology mapping algorithm for combinational circuits while assuming the positions of the flip-flops are fixed. We propose a new approach in which FFs can be arbitrarily repositioned by retiming. We present an efficient technology mapping algorithm that produces a mapping solution with the minimum clock period for a circuit without loops under the unit dealy model. The algorithm is also extended to the general delay model, in which case it produces a mapping solution with a clock period at most an interconnect or LUT delay away from the minimum one. Note that the algorithm can also be used for circuits with loops by removing some of the FFs to break the loops before the application of the algorithm. The superiority of our approach is further demonstrated experimentally.

关键词： Sequential circuits field programmable gate arrays

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The EPAC architecture: an expert cell approach to field programmable analog devices 96

The EPAC architecture: an expert cell approach to field prog...

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proceedings of the 1996 acm fourth international symposium on field-programmable gate arrays

作者： Hans W. Klein IMP Inc. San Jose CA

No abstract available.

ISBN: (纸本)9780897917735

No abstract available.

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Using BDDs to Design ULMs for FPGAs

Using BDDs to Design ULMs for FPGAs

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： Z. Zilic Z.G. Vranesic Department of ECE University of Toronto Canada

Many modern FPGAs use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. Since permutations and negation of signals are virtually costless operations in FPGAs, it is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have only recently been considered for application in FPGAs. In this paper we propose a class of ULMs useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on BDD description of logic functions. We give an explicit construction of a 3-input LUT replacement that requires only 5 programming bits, which is the optimum for such ULMs. A realistic size 4-input LUT replacement is obtained which uses 13 programming bits. Such logic blocks are especially important when FPGAs are used in a reconfigurable manner, because they can reduce the time and memory needed for changing the configuration.

关键词： Data structures Boolean functions field programmable gate arrays

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Emerald - An Architecture-Driven Tool Compiler for FPGAs

Emerald - An Architecture-Driven Tool Compiler for FPGAs

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： D.C. Cronquist L. McMurchie Department of Computer Engineering University of Washington Seattle WA USA

Ideally, the development phase of a new FPGA architecture would make use of a reliable set of mapping tools to produce accurate performance evaluations of proposed designs. Unfortunately, given the quick production time frames faced by most developers, tool construction is often postponed until after many architectural features have been frozen. To satisfy the need for fast tool prototyping, we have designed Emerald, a powerful architecture-driven system for quick development of FPGA tools. At its heart Emerald provides the basic features needed in all FPGA systems - logic block analysis, synthesis and technology mapping, global placement and partitioning, and detailed placement and routing. Its CAD environment provides an efficient way to thoroughly specify an FPGA's routing and logic block architectures, as well as architecture-specific metrics to tailor placement and routing. Moreover, Emerald's parameterized schematic specifications allow architectural veriations to be quickly captured and evaluated. The overall system is demonstrated on a bus-oriented sea-of-gates FPGA similar to the Atmel 6000.

关键词： field programmable gate arrays

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