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SceneMan: Bridging Mobile Apps with System Energy Manager via Scenario Notification 22

SceneMan: Bridging Mobile Apps with System Energy Manager vi...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Li, Li Wang, Jun Wang, Xiaorui Ye, Handong Hu, Ziang Ohio State Univ Columbus OH 43210 USA Huawei US R&D Santa Clara CA USA

ISBN: (纸本)9781509060238

Power management on current mobile devices relies on OS modules known as DVFS governors. However, existing governors determine system configuration only based on low-level information such as CPU load without any input about application-level behaviors. In particular, there exists no communication from mobile apps to energy managers. We find that information about app usage scenarios (e.g., gaming, video chatting) can usually help energy manager perform a better job and achieve more energy savings. Although app-level energy optimizations have been proposed, they generally focus on single usage scenarios and do not address optimization across multiple scenarios. In this paper, we propose SceneMan, an energy optimization framework for mobile apps based on usage scenario notification. SceneMan has three components: an API, a scenario notifier, and an energy manager. The key idea is to make energy managers aware of app-level scenarios. At runtime, apps notify the energy manager about their usage scenarios with provided APIs used by developers. The energy manager then takes appropriate actions to minimize energy consumption of the running scenario while meeting performance requirements. Energy optimization across scenarios can thus be easily achieved. The framework requires little extra programming effort and can help apps achieve better energy efficiency in a transparent way. We implement our system on a Nexus 6 smartphone and test it with 13 real-world apps under 2 usage scenarios, namely, gaming and video chatting. We achieve up to 33.2% energy savings with a worst-case performance loss of 5.1%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Online Tuning of Dynamic Power Management for Efficient Execution of Interactive Workloads 22

Online Tuning of Dynamic Power Management for Efficient Exec...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Bantock, James R. B. Tenentes, Vasileios Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Dept Elect & Comp Sci Southampton Hants England

ISBN: (纸本)9781509060238

Modern mobile devices contain powerful MultiProcessor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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RASP: A General Logic Synthesis System for SRAM-Based FPGAs

RASP: A General Logic Synthesis System for SRAM-Based FPGAs

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： J. Cong J. Peck Yuzheng Ding Department of Computer Science University of California Los Angeles CA USA AT and T Bell Laboratories Inc. Murray Hill NJ USA

In this paper, we present a general synthesis system for SRAM-based FPGAs named RASP. RASP consists of a core with a set of synthesis and optimization algorithms for technology independent logic synthesis and technology mapping for generating generic look-up tables (LUTs), together with a set of architecture-specific technology mapping routines to map the generic LUT network to programmable logic blocks (PLBs) for various SRAM-based FPGA architectures. Via a set of design representation converter routines, these architecture-independent and dependent synthesis algorithms are easily linked, and the entire system is seamlessly integrated into the design flow of commercial FPGA design systems. As a result, RASP can produce highly optimized designs for various SRAM-based FPGA architectures, and can be quickly adapted for new SRAM-based FPGA architectures. We compare RASP performance with that of several commercial synthesis systems on the MCNC logic synthesis benchmarks and a video compressor/decompressor. For almost all cases, RASP produces mapping solutions with significantly smaller critical path delay after place and route than current commercial synthesis systems.

关键词： field programmable gate arrays Network synthesis Table lookup Algorithm design and analysis programmable logic arrays programmable logic devices Design optimization Prototypes Computer science Video compression

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An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops 20

An Algorithm for Delay Optimal Logic Replication for FPGAs A...

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proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Rupesh S. Shelar Synopsys Inc. Hillsboro OR USA

ISBN: (纸本)9781450370998

Logic replication is often necessary to improve speed of emulation for systems employing field programmable gate arrays (FPGAs), since design sizes are large enough requiring partitioning to fit a design into multiple (boards of) FPGAs. In this paper, we propose a polynomial time algorithm for combinational logic replication that ensures delay optimality for directed acyclic graphs and reduces overhead due to look-up table (LUT) and cut resources. The algorithm is further extended to consider combinational loops, often yielding delay optimal results. Experimental results on industrial designs show, on an average, 44%, 33%, and 33% reduction in overhead due to cut, LUT costs, and runtimes, respectively, compared to existing heuristics, thus demonstrating the efficiency of the algorithm.

关键词： dynamic programming optimization prototyping field programmable gate arrays (fpgas) timing combinational loops logic replication emulation algorithm

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Universal Switch-Module Design for Symmetric-Array-Based FPGAs

Universal Switch-Module Design for Symmetric-Array-Based FPG...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： Yao-Wen Chang D.F. Wong C.K. Wong University of Technology Austin TX USA Department of Computer Science Chinese University of Hong Kong Hong Kong China

A switch module M with W terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (the number of nets on each side of M is at most W) is simultaneously routable through M. In this paper, we present a class of universal switch modules. Each of our switch modules has 6W switches and switch-module flexiblity three (Fs = 3). We prove that no switch module with less than 6W switches can be universal. We also compare our switch modules with those used in the Xilinx XC4000 family FPGA's and the anti-symmetric switch modules (with Fs = 3^1) suggested by [Flexibility of interconnection structures for field-programmable gate arrays]. Although these two kinds of switch modules also have Fs = 3 and 6W switches, we show that they are not universal. Based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25% more routing instances, compared with the XC4000-type one of the same size. Experimental results demonstrate that our universal switch modules improve routability at the chip level. Finally, our work also provides a theoretical insight into the important observation by Rose and Brown [Flexibility of interconnection structures for field-programmable gate arrays] that Fs = 3 is often sufficient to provide high routability.

关键词： field programmable gate arrays

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Research on Frequency Measurement Extractional Problem of a Certain Module Under High and Low Temperature 7

Research on Frequency Measurement Extractional Problem of a ...

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7th international symposium on Advances in Electrical, Electronics, and Computer Engineering

作者： Sun, Zhentao Department of Computer Jiangsu Automation Research Institute Lianyungang China

ISBN: (纸本)9781510656437

A certain type frequency measuring module appears in the measurement signal. In order to solve this problem, the design principle of the module is analyzed. Establish a fault tree, analyze the cause of the failure, and finalize the cause of the fault. The measurement frequency at a high and low temperature measurement frequency is 256 kHz. The measurement of the measured value is the measurement of the measured frequency, the resonance frequency stability is ± 30 * 10-6, and the measurement absolute accuracy is ± 1 Hz. Considering a variety of factors, it is recommended to replace the crystal and relax frequency measurement accuracy indicators to ± 8Hz without replacement of the frequency measurement accuracy index. © 2022 SPIE. All rights reserved.

关键词： field programmable gate arrays (FPGA)

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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (FPGA)

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 24

HLSFactory: A Framework Empowering High-Level Synthesis Data...

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6th international symposium on Machine Learning for CAD (MLCAD)

作者： Abi-Karam, Stefan Sarkar, Rishov Seigler, Allison Lowe, Sean Wei, Zhigang Chen, Hanqiu Rao, Nanditha John, Lizy Arora, Aman Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA Univ Texas Austin Austin TX USA Arizona State Univ Tempe AZ USA Int Inst Informat Technol Bangalore Bangalore Karnataka India

ISBN: (数字)9798350363562

ISBN: (纸本)9798400706998

Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible highquality HLS datasets and the complexity of building such datasets present great challenges to FPGA and ML researchers. Existing datasets either cover only a subset of previously published benchmarks, provide no way to enumerate optimization design spaces, are limited to a specific vendor, or have no reproducible and extensible software for dataset construction. Many works also lack user-friendly ways to add more designs to existing datasets, limiting wider adoption and sustainability of such datasets. In response to these challenges, we introduce HLSFactory, a comprehensive framework designed to facilitate the curation and generation of high-quality HLS design datasets. HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and FPGA tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage. This tripartite architecture not only ensures broad coverage of data points via design space expansion but also supports interoperability with tools from multiple vendors. Users can contribute to each stage easily by submitting their own HLS designs or synthesis results via provided user APIs. The framework is also flexible, allowing extensions at every step via user APIs with custom frontends, synthesis tools, and scripts. To demonstrate the framework functionality, we include an initial set of built-in base designs from PolyBench, MachSuite, Rosetta, CHStone, Kastner et al.'s Parallel Programming for FPGAs, and curated kernels from existing open-source HLS designs. We report the statistical analyses and design space

关键词： Solid modeling Statistical analysis Buildings Machine learning Benchmark testing Software Space exploration Sustainable development field programmable gate arrays Optimization

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The Wave Pipeline Effect on LUT-Based FPGA Architectures

The Wave Pipeline Effect on LUT-Based FPGA Architectures

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： E.I. Boemo S. Lopez-Buedo J.M. Meneses E.T.S.I. Telecomunicación Ciudad Universitaria Madrid Spain

The wave pipeline effect is based on the equalization of all path delays in order to allow several "waves" of data to travel along the circuit with a separation several times smaller than the maximum combinational delay of the circuit. The construction of wave pipelines requires gates and buffers with data-independent delay, and a well-characterized interconnection network delay model, in order to allow the equalization process to be managed by the designer. These features are inherently present in several RAM-based FPGAs architectures. Look-up tables (LUTs) permit the delay of digital blocks with different types of gates or different logic depth to be equalized; moreover, the delay of a FPGA interconnection network is completely parameterized and is a priori known. This paper describes a LUT-based wave pipeline array multiplier manually implemented using a Xilinx chip. The results show that, even for a single-phase non-skewed clocking strategy, a throughput as high as 85 MHz (measured) can be achieved, with 8 waves running in a 13-LUT logic depth combinational array with registered I/O, producing an initial latency of 9 clock cycles. For the FPGA architecture and the topology selected, such a large throughput/latency ratio would be impossible using classical pipelininig.

关键词： Pipelines field programmable gate arrays Propagation delay Delay effects Circuits Multiprocessor interconnection networks Clocks Throughput Logic arrays Table lookup

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