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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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Case study of convolutional neural network implemented on FPGA 4

Case study of convolutional neural network implemented on FP...

引用

4th international symposium on Power Electronics and Control Engineering, ISPECE 2021

作者： Zhong, Yicheng Zhang, Yong School of Mechanical and Electronic Engineering East China University of Technology Nanchang China

ISBN: (数字)9781510650374

ISBN: (纸本)9781510650367

Convolutional neural network (CNN) has become a key research area in artificial intelligent technology. A case study of garbage identification and classification using convolutional neural network is presented in this paper. The CNN model with five convolutional layers is used to extract feature maps from garbage pictures, and classifies six types of domestic garbage. ZYNQ-7020 is employed to deploy the CNN model in order to take advantage of high efficiency, low power consumption and flexibility of FPGA platform. Additionally, the classification results are obtained at the FPGA terminal by running Python code through PYNQ. The study demonstrates an efficient approach to practically deploy CNN model and implement image classification on FPGA platform. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： field programmable gate arrays (FPGA)

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FPGA-based HPC application design for non-experts (abstract only) 13

FPGA-based HPC application design for non-experts (abstract ...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

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Indirect connection aware attraction for FPGA clustering (abstract only) 13

Indirect connection aware attraction for FPGA clustering (ab...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Meng Yang Jiarong Tong A.E.A. Almaini State Key Lab of ASIC Fudan University Shanghai China Edinburgh Napier University Edinburgh United Kingdom

ISBN: (纸本)9781450318877

Indirect connection aware attraction clustering algorithm is proposed for clustered field programmable gate array architecture model to achieve simultaneously optimization of several performance metrics. A new cost function considers the attraction of the subsequent basic logic elements (BLEs) to the selected cluster, the number of the used pins already in the cluster, as well as critical path delay. The attractions of which BLEs are directly and indirectly connected to the selected cluster are taken into account. As a result, more external nets are absorbed into clusters, less number of pins per cluster and fewer clusters are required. Hence, smaller channel width is required for routing and speed of the design is improved. Performance comparisons are carried out in details with respect to state-of-the-art clustering techniques interconnect resource aware clustering (iRAC) and many-objective clustering (MO-Pack). Results show that the proposed algorithm outperforms these two clustering approaches with achievements of 38.8% and 42.2% respectively in terms of channel widths and 40.1% and 44.8% respectively in terms of number of external nets but with no critical path and area overhead.

关键词： FPGAs computer aided design clustering optimization field-programmable gate arrays

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Register leakage masking using Gray code

引用

2012 IEEE international symposium on Hardware-Oriented Security and Trust, HOST 2012

作者： Maghrebi, Houssem Guilley, Sylvain Prouff, Emmanuel Danger, Jean-Luc 37/39 rue Dareau 75 634 Paris Cedex 13 France 51 boulevard de La Tour-Maubourg 75 700 Paris France

ISBN: (纸本)9781467323390

Since their introduction in 1996, the effectiveness of side channel attacks has been highly improved and many countermeasures have been invalidated. A very common countermeasure consists in randomizing sensitive variables of algorithms by masking techniques. In this paper, we propose a new way to apply this strategy to secure hardware implementations of block ciphers. The main advantage of the proposed solution is that the masked variables and the masking material can be manipulated simultaneously without leaking sensitive information in the Hamming distance model. Moreover, we show that the leaking information stays very limited when the deterministic part of the real leakage slightly deviates from the Hamming distance. Finally, we apply our method to protect an AES hardware implementation and we show that the performances are suitable for practical implementations. © 2012 IEEE.

关键词： field programmable gate arrays (FPGA)

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A coarse-grained FPGA architecture for high-performance FIR filtering 98

A coarse-grained FPGA architecture for high-performance FIR ...

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proceedings of the 1998 acm/sigda sixth international symposium on field programmable gate arrays

作者： James R. Anderson Siddharth Sheth Kaushik Roy Intel Corporation 2200 Mission College Blvd. Santa Clara CA School of Electrical Engineering Purdue University West Lafayette IN

ISBN: (纸本)9780897919784

This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.

关键词： architecture finite impluse response filtering digital signal processing field programmable gate array

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Multi-channel video acquisition and storage technology based on GMSL

Multi-channel video acquisition and storage technology based...

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2022 international symposium on Artificial Intelligence Control and Application Technology, AICAT 2022

作者： Zhang, Xiaozheng Li, Mao Zhao, Haili Department of Information and Control Technology China North Vehicle Research Institute BeiJing China Laboratory 210 Changchun University of Science and Technology First Teaching Building Jilin Province Changchun China

ISBN: (纸本)9781510656710

In recent years, the rise of driverless technology makes the video transmission bandwidth of vehicle platform larger and larger. With the increase of the number of cameras used in cars, a large number of cameras will inevitably produce a large amount of data, which greatly increases the data bandwidth of the on-board platform. "Bandwidth"has become one of the biggest challenges faced by automobile manufacturers. This paper mainly studies the video acquisition and storage technology of multi-channel camera based on GMSL (Gigabit multimedia serial links), which can well solve the problem of data transmission bandwidth. Firstly, the principle of GMSL technology is studied;Secondly, taking FPGA processor as the core control chip, a multi-channel video acquisition and storage system based on GMSL is designed, the overall design scheme and hardware architecture are given, and the hardware circuit design of the system is completed;Finally, the technical feasibility of the system is verified, and the experimental effect of the system is good. © 2022 SPIE.

关键词： field programmable gate arrays (FPGA)

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Design of Reconfigurable Robot based on FPGA 7

Design of Reconfigurable Robot based on FPGA

引用

7th international symposium on Advances in Electrical, Electronics, and Computer Engineering

作者： Liu, Xinhao Wu, Zhanpeng Zhu, Zhanyang Liang, Xiaoyu School of Information Engineering Wuhan University of Technology Hubei Wuhan430070 China

ISBN: (纸本)9781510656437

A reconfigurable robot based on FPGA is designed and implemented in this project, which takes DE10_nano development board as the control core, integrates MPU-6500 gyroscope, ultrasonic module, photosensitive sensor, human body recognition module, and Openmv module, and expands the functions of obstacle avoidance, following, automatic light source tracking, human body recognition and so on. After many times of debugging, the automatic stabilization time of the robot is less than 2s after power on, and the obstacle avoidance function can be realized by automatically detecting objects in 10cm, recognizing the color of objects, and following them within the range of 20~30cm, automatically identifying light sources and tracking within 2m, and identifying the human body and alarm within 6m. © 2022 SPIE. All rights reserved.

关键词： field programmable gate arrays (FPGA)

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Optimized Modular Inversion Algorithm over Prime fields and Hardware Implementation 8

Optimized Modular Inversion Algorithm over Prime Fields and ...

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8th international symposium on Advances in Electrical, Electronics, and Computer Engineering, ISAEECE 2023

作者： Yu, Hao Yu, Zhe Han, Lin Zhongyuan University of Technology No. 1 Huaihe Road Xinzheng Zhengzhou451191 China National Supercomputing Center in Zhengzhou Zhengzhou450001 China

ISBN: (纸本)9781510666290

The modular inversion operations in the prime fields play an important role in the whole elliptic curve cryptosystem, and its operation speed directly determines the execution efficiency of the whole cryptosystem. The binary extended Euclidean algorithm in the existing general modular inversion algorithm is improved to obtain an optimized new algorithm. The new algorithm improves the shift efficiency of the original algorithm and reduces the cost of hardware resources. The 256-bit adder used in the new algorithm is split and reassembled, and the carry lookahead logic is used between groups. The addition and subtraction components are pipelined to improve data throughput. The algorithm is implemented using Verilog hardware description language and verified successfully on Virtex - 7 FPGA development board. The verification results show that the design can correctly handle 256-bit modular inversion operations, and the single calculation only consumes 1.12 μs. © 2023 SPIE. All rights reserved.

关键词： field programmable gate arrays (FPGA)

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Design of a light and high-resolution video camera system based on CMV12000 sensor 8

Design of a light and high-resolution video camera system ba...

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8th symposium on Novel Photoelectronic Detection Technology and Applications

作者： Nan, Nuo Zhou, Haian Li, Xin Tang, Qi Feng, Xingtai Yuan, Yuan Beijing Institute of Space Mechanics and Electricity Beijing100094 China

ISBN: (数字)9781510653122

ISBN: (纸本)9781510653115

To obtain the high-resolution and real-time digital image of the monitoring target and meet the requirements of miniaturization, a light and high-resolution video camera system based on FPGA is designed. The camera uses the large array CMOS sensor CMV12000 produced by the CMOSIS company and transfers the output data to the computer through Camlink interface. By using the FPGA as the core of timing control and completing the design of time-driving of CMOS sensor, output data remapping and Camlink interface with Verilog hardware language, the design of the camera is realized and a imaging experiment is carried out. The result shows that the driving sequence of the camera is reasonable and the communication with computer is correct. The camera operates stably and takes high quality images with the image resolution is 4096×3072. © 2022 SPIE

关键词： field programmable gate arrays (FPGA)

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An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

关键词： floating point exponential hpc fpga

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