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Design of video interface conversion system based on FPGA

Design of video interface conversion system based on FPGA

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international symposium on Optoelectronic Technology and Application 2014: Image Processing and Pattern Recognition, IPTA 2014

作者： Heng, Zhao Wang, Xiang-Jun State Key Laboratory of Precision Measuring Technology and Instruments Tianjin University Tianjin300072 China MOEMS Education Ministry Key Laboratory Tianjin University Tianjin300072 China

ISBN: (纸本)9781628413878

This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor. The current experiment shows that it can achieve high-quality video conversion with minimum board size. © 2014 SPIE.

关键词： field programmable gate arrays (FPGA)

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Are FPGAs suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

FPGAs constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the FPGA community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current FPGA market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for FPGA-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the FPGA industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

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HexCell: a Hexagonal Cell for Evolvable Systolic arrays on FPGAs: (Abstract Only) 18

HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on F...

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proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Fady Hussein Luka Daoud Nader Rafla Boise State University Boise ID USA

ISBN: (纸本)9781450356145

This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent configuration schemes: dynamic partial reconfiguration (DPR), where the functional unit is partially reconfigured at run time, and virtual reconfiguration circuit (VRC), where the cell output port bypasses one of the input data or selects the functional unit output. Hence, HexCell combines the merits of DPR and VRC including resource-awareness, reconfiguration speed and routing flexibility. In addition, the cell structure supports pipelining and data synchronization for achieving high throughput for data-intensive applications like image processing. A HexCell is represented by a binary string (chromosome) that encodes the cell's function and the output selections. Our developed evolvable HexCell array supports more inputs and outputs, a variety of possible datapaths, and has faster reconfiguration, compared to the state-of-the-art systolic array while maintaining the same resource utilization. Moreover, by using the same genetic algorithm on the two systolic arrays, results show that the HexCell array has higher throughput and can evolve faster than state-of-the-art array.

关键词： fpga hexcell systolic arrays dynamic partial reconfiguration (dpr) evolvable hardware virtual reconfiguration circuit (vrc)

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AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator 24

AutoHammer: Breaking the Compilation Wall Between Deep Neura...

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proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Kai Qian Zheng Liu Yinqiu Liu Haodong Lu Zexu Zhang Ruiqiu Chen Kun Wang Fudan University Shanghai China Nanyang Technological University Singpore Singapore Fudan University Shanghaii China

ISBN: (纸本)9798400704185

field-programmable gate Array (FPGA) has shown great potential in accelerating Deep Neural Networks (DNNs) due to its characteristics of programmability and high power efficiency. In address the compilation challenges between DNNs and FPGA, we propose AutoHammer, an automated compiler for mapping DNNs to different FPGAs. Specifically, AutoHammer leverages overlay techniques to enable fast and effective implementation. Moreover, three enablers are integrated into AutoHammer. First, the Model Translator optimizes the topology and predicts a DNN's results based on different hardware configurations, built on top of a topology-based representation of DNNs. Second, the Instruction Generator generates pipeline data streams in various FPGA resource configurations by manipulating the instruction set at the upper level rapidly. Last, we realize the End-to-end Optimization, moving the whole computational processes onto the FPGA. Extensive experimental results show that AutoHammer improves great deployment efficiency when validated by 14 types of DNN models on 3 companies' (Xilinx, Fudan Micro, and Pango Micro) mainstream FPGA chips.

关键词： compiler deep neural networks field-programmable gate array (fpga)

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Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity 19

Embracing Systolic: Super Systolization of Large-Scale Circu...

引用

proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Jiafeng Xie Chiou-Yng Lee Villanova University Villanova PA USA Lunghwa University of Science and Technology Taoyuan Taiwan Roc

ISBN: (纸本)9781450361378

The recent advance in artificial intelligence (AI) technology has led to a new round of systolic structure innovation. Many AI accelerators have employed systolic structure to realize the core large-scale matrix-vector multiplication for high-performance processing, which has a complexity of $o(n^2)$ for matrix size of $n\times n$ (difficult to be implemented on the field-programmable gate array (FPGA) platform). To overcome this drawback, in this paper, we propose a super systolization strategy to implement the core circulant matrix-vector multiplication into a systolic structure with subquadratic space complexity. The proposed effort is carried out through two stages of coherent interdependent efforts: (i) a novel matrix-vector multiplication algorithm based on Toeplitz matrix-vector product (TMVP) approach is proposed to obtain subquadratic space complexity; (ii) a series of optimization techniques are introduced to map the proposed algorithm into desired systolic structure. Finally, detailed complexity analysis and comparison have been conducted to prove the efficiency of the proposed strategy. The proposed strategy is highly efficient and can be extended in many neural network based hardware implementation platforms.

关键词： field-programmable gate array systolic structure large-scale toeplitz matrix vector product circulant matrix-vector multiplication subquadratic space complexity

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The design of a low energy FPGA 99

The design of a low energy FPGA

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international symposium on Low Power Electronics and Design (ISLPED)

作者： V. George Hui Zhang J. Rabaey Berkeley Wireless Research Center University of California Berkeley CA USA

ISBN: (纸本)9781581131338

This work presents the design of an energy efficient FPGA architecture. Significant reduction in the energy consumption is achieved by tackling both circuit design and architecture optimization issues concurrently. A hybrid interconnect structure incorporating nearest neighbor connections, symmetric mesh architecture, and hierarchical connectivity is used. The energy of the interconnect is also reduced by employing low-swing circuit techniques. These techniques have been employed to design and fabricate an FPGA. Preliminary analysis show energy improvement of more than an order of magnitude when compared to existing commercial architectures.

关键词： field programmable gate arrays Integrated circuit interconnections Computer architecture Power dissipation Energy efficiency Energy consumption Clocks Frequency Logic Switches

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FPGA implementation of highly parallelized decoder logic for network coding (abstract only) 10

FPGA implementation of highly parallelized decoder logic for...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunwoo Kim Won W. Ro Yonsei University Seoul South Korea

ISBN: (纸本)9781605589114

Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmable gate-array (FPGA). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. The decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. The performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.

关键词： network coding fpga fpga implementation galois field arithmetic

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CReconfigurable finite field instruction set architecture 07

CReconfigurable finite field instruction set architecture

引用

proceedings of the 2007 acm/sigda 15th international symposium on field programmable gate arrays

作者： Nathan Jachimie Fernando Martinez-Vallin Jafar Saniie Illinois Institute of Technology Chicago Illinois

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： FSL instruction set extensions Xilinx fast simplex links galois fields MicroBlaze embedded development partial reconfiguration finite field arithmetic

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On - orbit maintenance and reconfiguration of DSP based on FPGA 2

On - orbit maintenance and reconfiguration of DSP based on F...

引用

2nd international symposium on Computer Technology and Information Science, ISCTIS 2022

作者： Ren, Hongxuan Liu, Han Xue, Qiang Ma, Xiaoqing Jiang, Tong Sun, Baohua Xi'an China

ISBN: (纸本)9781510660533

FPGA+DSP architecture is widely used in satellite digital processing systems. The satellite is in an environment where there is a lot of particle radiation and collisions. In order to avoid changes in stored code data brought by SEU (Single Event Upset), improve the system reliability, at the same time meet the current requirements of software on-orbit reconfiguration, the FPGA and DSP in the space-borne core processor need to have the ability of error correction and reconfiguration. To do this, FPGA and DSP programs need to be stored in external, writable memory. Nor Flash, with its high capacity and reliability, is often chosen as the memory for storing code. At present, the on-orbit maintenance of FPGA is usually realized by using Actel FPGA to conduct TMR (Triple Modular Redundancy), refresh and other processing on the FPGA code stored in Flash. Based on this idea, a T-shaped structure is constructed among FPGA, DSP and Flash for the architecture of the space-borne processor. As the master, FPGA controls Flash to complete TMR, error correction and on-orbit reconfiguration of DSP code. This method reduces hardware redundancy, gives consideration to autonomous maintenance and on-orbit reconfiguration, and increases system robustness. This method has been applied and fully verified in orbit. © 2022 SPIE.

关键词： field programmable gate arrays (FPGA)

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A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

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proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. This architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. Through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). These switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

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