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检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

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Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only) 14

Methodology to generate multi-dimensional systolic arrays fo...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Nick Ni Embedded Applications Engineer Altera Corporation San Jose CA USA

ISBN: (纸本)9781450326711

Systolic arrays (SA) in a FPGA provide a significant speed up on many scientific calculations through massive parallelism exploitation. The low-level hardware design of such complex SA is becoming more time-consuming and non-scalable with more transistors being available on a single chip. In this paper we present a novel methodology to generate multi-dimensional SA for FPGAs using a well-accepted high-level language, OpenCL. Kernels written in OpenCL can then be compiled directly into hardware using an OpenCL high-level synthesis tool. A complex case study using our methodology is presented. We were able to design, generate, verify and optimize the entire FPGA based hardware accelerator using the Smith-Waterman, in only three man weeks. The accelerator's top performance was 32.6 GCUPS (Giga-Cell-Updates-Per-Second) on a DNA similarity search with 1.3 GCUPS/watt efficiency. The result is superior to most state-of-the-art CPU/GPU implementations and competitive against a hand-crafted hardware design which took many months to develop.

关键词： high-level synthesis bioinformatics productivity smith-waterman opencl fpga systolic arrays generation algorithm

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Stochastic-Based Spin-programmable gate Array with Emerging MTJ Device Technology (Abstract Only) 16

Stochastic-Based Spin-Programmable Gate Array with Emerging ...

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proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Yu Bai Mingjie Lin University of Central Florida Orlando FL USA

ISBN: (纸本)9781450338561

This paper describes the stochastic-based Spin-programmable gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in FPGAs, our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure. Our mixed mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10x improvement in logic density, about 5x improvement in average net delay, and about 5x improvement in the critical path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.

关键词： stochastic fpga emerging devices

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Logic gates in the routing network of FPGAs (Abstract Only) 15

Logic Gates in the routing network of FPGAs (Abstract Only)

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Elias Vansteenkiste Berg Severens Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781450333153

We propose a new kind of FPGA architecture with a routing network that not only provides interconnections between the functional blocks but also performs some logic operation. More specifically we replaced the routing multiplexer node in the conventional architecture with an element that can be used as both AND gate and multiplexer. A conventional routing multiplexer node consists of a multiplexer and a two stage buffer. In our new architecture a NAND gate replaces the first inverter stage of the buffer and two multiplexers half the size of the original multiplexer replace the original multiplexer. The aim of this study is to determine if this kind of architecture is feasible and if it is worth to implement pack, placement and routing tools in the future. We developed a new technology-mapping algorithm and sized the transistors in this new architecture to evaluate the area and delay. Preliminary results indicate that the gain in logic depth and area achieved by mapping to not only LUTs but also to AND gates outweighs the overhead of introducing AND gates in the routing network with a net reduction in area-delay product of 5.6. Designs implemented on the proposed architecture would require 11.2 % more area, but they will have a 14 % decreased logic depth and the architecture has a slightly faster representative critical path. These results are preliminary because the pack, place and route routines are not implemented yet.

关键词： transistor sizing technology mapping routing nodes programmable interconnection architecture logic gates

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Scalable architecture for programmable quantum gate array (abstract only) 10

Scalable architecture for programmable quantum gate array (a...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Mingjie Lin Yaling Ma UC Berkeley Berkeley CA USA UC Berkeley Berkeley USA

ISBN: (纸本)9781605589114

This work explores architectural ideas to build a scalable programmable quantum gate array (PQGA) by exploiting unique quantum effects such as superposition and entanglement/teleportation. In contrast to prior studies, in which a quantum computing machine is implemented either as an ASIC-like special-purpose chip tailored for specific algorithm or as a general-purpose processor based on the Von-Neumann model, we propose a PQGA architecture that is reconfigurable for different domain-specific applications with high logic density. The PQGA architecture is novel in several aspects, among which its interconnect work is built with "virtual wires" implemented with quantum entanglement. In this work, we propose various designs for logic block, interconnect network, and design strategies to construct large designs in PQGA. Our goal is to investigate new architectural ideas based on reconfigurable computing method in order to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum comput- ing. Leveraging the extensive groundwork in quantum computing and algorithm design, we provide estimation results to show that our proposed PQGA architecture can achieve not only high performance but also scalability. Finally, we benchmark our proposed PQGA architecture against previous quantum computer architecture and illustrate on average a 3x improvement in terms of logic density for the well-known Shor's quantum factoring algorithm.

关键词： reconfigurable computing quantum

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only) 11

Memory based computing: reshaping the fine-grained logic in ...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Somnath Paul Swarup Bhunia Case Western Reserve University Cleveland OH USA

ISBN: (纸本)9781450305549

Conventional field programmable gate Array (FPGA) architectures leverage on the purely spatial computing model where a design is realized in the form of a small multiple-input single-output lookup tables (LUTs) connected through programmable interconnect switches. However, such a model incorporates an elaborate programmable interconnect network which becomes a major performance bottleneck and leads to poor scalability across process technology nodes. In this paper we evaluate an alternative two-dimensional static random access memory (SRAM) array based reconfigurable computing fabric, referred to as "Memory Based Computing" (MBC) that departs from a purely spatial architecture by advocating multi-cycle evaluation at each computational element. Within a computational element, it uses a dense two-dimensional SRAM array to map large multi-input multi-output functions as LUT and evaluate them in time-multiplexed topological fashion. Multi-cycle execution at each computing node is accomplished using a local interconnect architecture. The proposed framework substantially reduces the requirement for global interconnects by folding computational resources onto a single computational element. We explore the design space for MBC to optimize the major design parameters and compare the performance, power dissipation and energy-delay product for benchmark applications between MBC and conventional SRAM-based FPGA. Simulation results show that compared to a clustered FPGA model, the proposed framework achieves 57% improvement in performance, 30% improvement in Energy Delay Product (EDP) and 10% improvement in technological scalability of performance for standard benchmark circuits. Finally, we validate the functionality of MBC framework and timing of different operations by mapping several small applications on a Cyclone III FPGA platform from Altera.

关键词： memory based computation field programmable gate array (fpga) recongurable hardware

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory 24

Design and Implementation of a Primary Visual Cortex Pathway...

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proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Hui Wei Jingyong Ye Yutong Chen Heng Wu Fudan University Shanghai China University of Science and Technology of China Hefei China

ISBN: (纸本)9798400704185

Neurobiology has made groundbreaking discoveries that have propelled the development of brain-inspired computing. This new field of research has led to the creation of neural pathways that mirror the human brain's visual system, providing numerous transformative insights for modern image processing. Brain-like vision offers remarkable processing efficiency and promises a range of exciting applications, from enhancing video surveillance to improving medical diagnosis. However, current brain-inspired computing models lack portability and efficient power consumption, which limits their widespread use. To address these challenges, we've designed a brain-like color opponent multi-layer neural network model on field programmable gate arrays (FPGAs). This innovative approach enhances portability, reduces power consumption, and increases parallelism in the brain-like computational model. We've conducted rigorous experiments on natural images, and the results are promising. FPGAs can further enhance this innovative approach by improving computational parallelism and enhancing the display of crucial structural information while downplaying trivial details. This integration of biological mechanisms into practical embedded systems is a significant step towards merging these two technologies. Our multi-layer neural network structure aligns with FPGAs' in-memory computing mechanism, bridging the gap between these two technologies. Our work represents a step towards merging them and utilizes physiological color opponent theory to enhance FPGAs' effectiveness in practical image processing applications. By combining the power of neurobiology with the flexibility of FPGAs, we can create more efficient and practical solutions for image processing tasks in various fields.

关键词： brain-like vision neurovisual pathways opponent-process programmable devices

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FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only) 15

FiT: An Automated Toolkit for Matching Processor Architectur...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Charles Mutigwe Johnson Kinyua Farhad Aghdasi NxCORES Research East Longmeadow MA USA Virginia International University Fairfax VA USA University of Fort Hare Alice South Africa

ISBN: (纸本)9781450333153

As the complexity of designing electronic systems continues to grow, the most commonly used solution has been to move the design process to higher levels of abstraction via software tools. In this work we present one such tool that can be used to automatically generate custom processors and systems-on-chip (SoC) from C source code or application binary files, with no requirement for the user to understand any of the underlying hardware systems. This tool also does not call for the application to be profiled for any 'hot spots' as a prerequisite for generating the custom processor. We use the toolkit to generate two types of custom processors; the area-optimized processors and the performance-optimized processors. We study the resource utilization of the custom processors and compare them with those predicted by the core density model. We find that the performance-optimized processor results are as predicted by the core density model.

关键词： electronic system level (esl) design application-specific soft processor reconfigurable computing c-to-silicon compiler

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Power-aware FPGA technology mapping for programmable-VT architectures (abstract only) 12

Power-aware FPGA technology mapping for programmable-VT arch...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wei Ting Loke Yajun Ha Xilinx Asia Pacific Pte. Ltd. & National University of Singapore Singapore Singapore National University of Singapore Singapore Singapore

ISBN: (纸本)9781450311557

In this paper, we present a framework for leakage power reduction in FPGAs with programmable-VT architectures, with focus on dual-VT technology mapping. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the possible strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to tune LUT VT via RBB offer the potential of reducing leakage power with no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs oer some levels of VT programmability, but with optimizations limited to the post-P&R stage. We present a novel technology mapper (RBBMap), logic block packer (RBBPack) and placement-and-routing tool (RBBVPR) that together demonstrate the advantages in moving RBB optimizations upwards to the technology mapping level. Compared to an existing power-optimized technology mapping tool Emap, our framework oers an average of 44.41% savings in average logic block leakage power and 30.88% savings in average total energy consumption. We also illustrate why our work is potentially superior to another comparable work DVMap-2 that utilizes a dual-VDD approach.

关键词： fpga multiple voltage programmable-vt dual-vt reverse back bias technology mapping

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A field programmable array core for image processing (abstract only) 12

A field programmable array core for image processing (abstra...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Declan Walsh Piotr Dudek The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450311557

Massively parallel processor arrays have been shown to be an effective and suitable choice for image processing tasks [1]. More recently, some of the state of the art processor arrays have been used for real-time machine vision tasks such as intelligent transport system applications [2] or video processing on mobile applications [3] providing a much more powerful solution than a conventional processor. A number of Single Instruction Multiple Data (SIMD) processor arrays have been implemented on FPGAs [4]-[6], which are particularly suited to implementing such processor architectures because of their similarities of both being arrays of fine grained logic elements. In this work, we propose an FPGA implementation of a processor array where the processing elements (PEs) are as small as possible, while providing local memory sufficient for processing greyscale images. The PE is then replicated to form an array. A 32 × 32 PE array is implemented on a Xilinx Virtex 5 XC5VLX50 FPGA using the four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 96 MHz and executes a peak of 98.3 giga operations per second (GOPS) (bit-serial operations). A binary edge detection algorithm is performed in 52.08 ns. Uploading and downloading a binary image in a 32 × 32 array takes an extra 687.5 ns. Sobel edge detection of an 8-bit greyscale image is performed in 5.33 µs. Uploading and downloading an 8-bit greyscale image in a 32 × 32 array takes 5.36 µs. With larger FPGAs being available in the future, the array sizes comparable to state of the art custom designed ICs can be implemented on these FPGAs.

关键词： architecture fpga simd image processor array

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