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On Feasibility of FPGAs Without Dedicated programmable Interconnect Structure 19

On Feasibility of FPGAs Without Dedicated Programmable Inter...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Anastasiia Kucherenko Stefan Nikolic Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781450361378

It is a well known fact that a great majority of FPGA chip area goes into the programmable interconnect structure. Since area consumption is mostly proportional to the level of flexibility the interconnect structure offers, how much of this flexibility is really needed for the implementation of any design of interest is a logical question to pose. Going one step further, one may wonder if a dedicated programmable interconnect structure is even necessary. This work answers exactly this second question by providing constructive capability proofs, for a broad class of FPGA architectures composed solely of look-up tables (LUTs) connected in a fixed manner, to implement any circuit graph. Our proposed architectures consist of identical cells of LUTs with fixed connections, arranged on a 2D grid. Direct wires between cell input and output pins are also allowed, enabling long uninterrupted connections. We begin by formalizing the above architecture class, and then describe an algorithm capable of mapping any circuit on one specific member of it, in which each cell consists of a single 4-LUT. We derive area and runtime bounds for the algorithm, and finally extend it to be applicable to any architecture in which no LUT receives more than K - 4 inputs from within the cell (K is LUT size) and the number of sink LUTs of the cell does not exceed the number of source LUTs. Presented algorithms serve to answer the posed question, but, due to area-inefficiency, do not have much practical value at this point.

关键词： periodic graphs routing algorithms universality proofs fixed interconnect hard-wired fpgas

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A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based Accelerators 23

A Flexible Toolflow for Mapping CNN Models to High Performan...

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Yongzheng Chen Gang Wu Northeastern University Shenyang China

ISBN: (纸本)9781450394178

There have been many studies on developing automatic tools for mapping CNN models onto FPGAs. However, challenges remain in designing an easy-to-use toolflow. First, the toolflow should be able to handle models exported from various deep learning frameworks and models with different topologies. Second, the hardware architecture should make better use of on-chip resources to achieve high performance. In this work, we build a toolflow upon Open Neural Network Exchange (ONNX) IR to support different DL frameworks. We also try to maximize the overall throughput via multiple hardware-level efforts. We propose to accelerate the convolution operation by applying parallelism not only at the input and output channel level, but also at the output feature map level. Several on-chip buffers and corresponding management algorithms are also designed to leverage abundant memory resources. Moreover, we employ a fully pipelined systolic array running at 400 MHz as the convolution engine, and develop a dedicated bus to implement the im2col algorithm and provide feature inputs to the systolic array. We generated 4 accelerators with different systolic array shapes and compiled 12 CNN models for each accelerator. Deployed on a Xilinx VCU118 evaluation board, the performance of convolutional layers can reach 3267.61 GOPS, which is 99.72% of the ideal throughput (3276.8 GOPS). We also achieve an overall throughput of up to 2424.73 GOPS. Compared with previous studies, our toolflow is more user-friendly. The end-to-end performance of the generated accelerators is also better than that of related work at the same DSP utilization.

关键词： field-programmable gate array (FPGA) toolflow convolutional neural network (CNN) systolic array memory management

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Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only) 15

Architecture of Reconfigurable-Logic Cell Array with Atom Sw...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Xu Bai Yukihide Tsuji Ayuka Morioka Makoto Miyamura Toshi Sakamoto Munehiro Tada Naoki Banno Koichiro Okamoto Noriyuki Iguchi Hiromitsu Hada Low-power Electronics Association & Project (LEAP) Tsukuba Japan

ISBN: (纸本)9781450333153

Emerging nonvolatile memories (NVMs) have a potential to overcome the issues in the conventional static random-access memory (SRAM) based reconfigurable logic cell arrays (RLCAs). Replacing a CMOS switch element composed of a SRAM and a pass transistor by a NVM reduces chip size. And non-volatility reduces the stand-by power. More importantly, the compactness of NVM allows fine-grain logic cells (small cluster size), which advantageously enables a highly efficient cell usage, resulting in compact circuit for applications. In this paper, we investigate the fine-grain cell architecture using atom switch which is one of the NVMs. We evaluate the effect of the cluster size and the segment length on the atom-switch-based RLCA to confirm the optimal point considering area-delay product. Cluster size is optimized to be 4, which is smaller than that in the conventional SRAM- and multiplexer-based RLCA. This optimization is originated from the fact that the inter-delay among clusters is only twice of the intra-delay in cluster for atom-switch-based RLCA with routing block formed by crossbar switches because of very small capacitance and resistance of atom switches. On the other hand, the segment length is optimized to be 4, which is the same as that in the conventional SRAM- and multiplexer-based RLCA.

关键词： programmable logic routing fabrics cross bar switch atom switch cluster nonvolatile

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A DSP and FPGA based integrated controller development solutions for high performance electric drives

A DSP and FPGA based integrated controller development solut...

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IEEE international symposium on Industrial Electronics (ISIE)

作者： Z. Bielewicz L. Debowski E. Lowiec The Gdańsk Branch Electrotechnical Institute GdaDsk Poland

Modern drive control algorithms require advanced hardware and software platforms suitable for fast, efficient and reliable implementations. The development process includes in most cases the following engineering steps: off-line software simulations, hardware design and software implementation in a target system. This paper presents the general requirements connected with microprocessor-based digital control systems for drive control applications. An integrated and flexible hardware and software environment for electric drives control is described. The hardware part of the system includes flexible stand-alone boards and PC-cards set based on the digital signal processors (DSP) family and advanced field programmable gate arrays (FPGA). The flexibility of FPGAs provides multiprocessor and open architecture interface. The PC-based simulation environment offers hardware-in-the-loop options and extended data acquisition functions. After simulation and evaluation procedures the software structure of the controllers can be transfered into the stand-alone DSP board ready for commercial application. The proposed integrated system is very useful in the high-performance AC drives and double-fed machine controller designs. Currently, the project of the DSP controller for the voltage source inverter with the power range above 100 kW is under way in the Gdansk Branch of the Electrotechnical Institute. Several simulation and experimental results are presented and summarised.

关键词： Digital signal processing field programmable gate arrays Hardware Control systems Application software Software algorithms Signal processing algorithms Reliability engineering Design engineering Software design

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HMLib: Efficient Data Transfer for HLS Using Host Memory 23

HMLib: Efficient Data Transfer for HLS Using Host Memory

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA Inha University Incheon Republic of Korea

ISBN: (纸本)9781450394178

Streaming applications compose an important portion of the workloads that FPGAs may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the FPGA DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the FPGA's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.

关键词： high-level synthesis field-programmable gate array on-chip memory host memory opencl streaming workload

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The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop 11

The role of FPGAs in a converged future with heterogeneous p...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jonathan Rose Guy Lemieux University of Toronto Toronto ON Canada University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

The battle of fixed function devices vs. programmable devices has been won by the programmables. The question facing us now is to determine what kinds of programmability to place on next generation systems/devices. Research and development on many applications has shown that different kinds of hardware and software programmability succeed for different application classes: powerful, singlethread-optimized CPUs continue to do very well for many applications; the General Purpose GPU is carving a niche in high throughput, parallel floating point codes in addition to its home turf of graphics; the FPGA is particularly good at variable bit-size computations and data steering, as well as parallel distributed control of networks. Future systems may well need all three types of these types of engines, and perhaps interesting mixtures of them. This is particularly true when we deal with the combined goals of optimizing cost, performance and *** this workshop, we will look to the future of the FPGA within these types of 'converged' programmable computing engines, and reflectively ask ourselves: What role can the FPGA play? What future applications in areas such as networking, mobile, and artificial intelligence can be driven by FPGAs? How do FPGAs fit into the architecture realm of CPUs, general purpose GPUs, and DSPs? How should the designer/programme express their intent in the most effective way possible? What are the requirements for a compilation and optimization environment that allow FPGAs to intermix within a heterogeneous and converged future?The intent of this workshop is to open a discussion on these questions. There will be a series of short, invited talks interspersed with free and open discussion.

关键词： heterogeneity reconfigurable computing high level programming models fpga heterogeneous computing systems signal processing dsp

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A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory arrays (Abstract Only) 15

A Hardware Implementation of a Unit for Geometric Algebra Op...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Gerardo Soria García Adrian Pedroza de la Cruz Susana Ortega Cisneros Juan José Raygoza Panduro Eduardo Bayro Corrochano Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional Zapopan Mexico Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional zapopan Mexico Universidad de Guadalajara Guadalajara Mexico

ISBN: (纸本)9781450333153

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

关键词： fpga address generator geometric product. geometric algebra memory arrays

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Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS 19

Efficient FPGA Implementation of Conjugate Gradient Methods ...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Sahithi Rampalli Natasha Sehgal Ishita Bindlish Tanya Tyagi Pawan Kumar International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450361378

In conjugate gradient method to solve partial differential equations, matrix vector operations are required in each iteration; these matrix vector operations can be implemented as 5 point finite difference stencil operations on the grid without explicitely constructing the matrix. We show that a pipelined and superscalar design using high level synthesis (HLS) leads to a significant reduction in latencies for two variants of conjugate gradient methods considered. When comparing these two, we show that the second method has roughly two times lower latency than the former given the same degree of superscalarity. These reductions in latencies for the newer variant of CG is due to parallel implementations of stencil operation on subdomains of the grid, and due to overlap of these stencil operations with dot product operations. In a superscalar design for the stencil operation, the computational domain needs to be partitioned, and boundary data needs to be copied, which requires padding. We propose a novel traversal of the grid for 2D domain decomposition that leads to reduction in latency cost involved with padding. The FPGA implementation of CG is roughly 7 times faster than state-of- the-art sequential implementation, and roughly 4 times faster than state-of-the-art CUDA library parallel implementation for the linear system of dimension 10000 x 10000.

关键词： fpga high level synthesis laplace system pipelining superscalarity conjugate gradient

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High Density Pipelined 8bit Multiplier Systolic arrays for FPGA 20

High Density Pipelined 8bit Multiplier Systolic Arrays for F...

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proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Martin Langhammer Sergey Gribok Gregg Baeckler Intel Marlow United Kingdom Intel San Jose CA USA

ISBN: (纸本)9781450370998

With the advent of AI and machine learning as the highest profile FPGA applications, INT8 performance is currently one of the key benchmarking metrics. In current devices, INT8 multipliers must be extracted from higher precision multipliers. Recently, we reported the implementation of a mixed DSP Block and soft logic design, with 22,400 INT8 multipliers, and a system clock rate of 416MHz, on the Intel Stratix 10 2800 *** this paper we demonstrate alternate techniques for integer multiplier construction to better balance the resource types on current FPGAs - logic, memory, and DSP - to make a significant improvement in the multiplier, and therefore the dot product, density. We further extend these techniques to 8 bit signed-magnitude (SM) 1.7 representation, which can further improve arithmetic density by using the logic and memory resources more flexibly. We describe variable composition dot product structures, which can be assembled in a scalable 2D systolic array. In one example, we report a design containing 32,768 SM1.7 multipliers, with a clock rate of 432MHz, giving a system performance of over 28 TOPs. Our INT8 densities are improved by up to 30% over the earlier work - we show one design with 28,800 INT8 multipliers. In all cases, enough device resources are left free and accessible to implement a full application level design.

关键词： int8 array fpga multiplier

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Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only) 16

Re-targeting Optimization Sequences from Scalar Processors t...

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proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Ronak Kogta Suresh Purini Ajit Mathew International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450338561

A high-level synthesis compiler translates a source program written in a high level programming language such as C or SystemC into an equivalent circuit. The performance of the generated circuit in terms of metrics such as area, frequency and clock cycles depends on the compiler optimizations enabled and their order of application. Finding an optimal sequence for a given program is a hard combinatorial optimization problem. In this paper, we propose a practical and search time efficient technique for finding a near-optimal sequence for a given program. The main idea is to strike a balance between the search for a universally good sequence (like that of O3) which works for all programs vis-a-vis finding a good sequence on a per-program basis. Towards that, we construct a rich downsampled sequence set, which caters to different program classes, from the unbounded optimization sequence space by applying heuristic search algorithms on a set of Microkernel benchmark programs. The optimization metric that we use while constructing the downsampled sequence set is the execution time on a scalar processor. Given a new program, we try all the sequences from the downsampled sequence setand pick the best. Applying this technique in the LegUp high-level synthesis compiler, we are able to obtain 23% and 40% improvement on CHStone and Machsuite benchmark programs respectively. We also propose techniques to further reduce the size of the downsampled sequence set to improve the sequence search time.

关键词： high level synthesis optimization compilers

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