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Efficient tiling patterns for reconfigurable gate arrays 08

Efficient tiling patterns for reconfigurable gate arrays

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proceedings of the 16th international acm/sigda symposium on field programmable gate arrays

作者： Sumanta Chaudhuri Jean-Luc Danger Philippe Hoogvorst Sylvain Guilley ENST Paris France

ISBN: (纸本)9781595939340

This article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in FPGAs. The goal of our research is to evolve FPGA architectures with advances in technology, and specifically better utilization of available interconnect layers. We propose a method to evaluate tiling patterns based on the first principles ( i.e Rent's Rule, Donath's result, equivalence of wire flux and wire length). We show that, use of tiling patterns formed with higher order polygons can improve the speed and area performances of an FPGA. This gain is highly dependent on depopulation schemes and other parameters. However for generic tiling patterns with crossbar switchboxes there is a 22% gain in area for the hexagonal tiling pattern, and a 30% gain in area for the octagonal tiling pattern. Moreover the average interconnect length is around 15% lesser for hexagonal and 31% lesser for the octagonal tiling compared to square tiling. We can expect a proportional increase in speed. We also present a comparative plot of total interconnect lengths for these tiling patterns and the hierarchical gate arraysThe physical realizability of these tiling patterns in CMOS are to be investigated. We present a layout scheme for both hexagonal and octagonal FPGAs. To our knowledge standard processes support 45° metal lines, whereas 60° lines can be etched using non-standard processes. We must keep in mind, that in practice one must use some sort of depopulation and staggering scheme, and these results provide only an idea of gains that can be achieved. The actual interconnect structure is of course dependent on several factors (i.e available interconnect layers, difficulty of fabrication, required speed/area, evolution of CMOS technology etc). Our future research direction will be to choose an efficient interconnect strategy based on this and previous researches, as well as experimental results

关键词： tiling interconnect FPGA hexagonal octagonal

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A method to represent multiple-output switching functions by using multi-valued decision diagrams

A method to represent multiple-output switching functions by...

引用

international symposium on Multiple-Valued Logic

作者： T. Sasao J.T. Butler Department of Computer Science and Electronics Kyushu Institute of Technology Iizuka Japan Department of Electrical and Computer Engineering Naval Postgraduate School Monterrey CA USA

Multiple-output switching functions can be simulated by multiple-valued decision diagrams (MDDs) at a significant reduction in computation time. analyze the following approaches to the representation problem: shared multiple-valued decision diagrams (SMDDs), multi-terminal multiple-valued decision diagrams (MTMDDs), and shared multi-terminal multiple-valued decision diagrams(SMTMDDs). For example, we show that SMDDs fend to be compact, while SMTMDDs tend to be fast. We present an algorithm for grouping input variables and output functions in the MDDs.

关键词： Data structures Boolean functions Input variables Logic functions Binary decision diagrams Table lookup Logic testing field programmable gate arrays Computer science Time sharing computer systems

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Verification of the Sparrow processor

Verification of the Sparrow processor

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international Conference and Workshop on Engineering of Computer-Based Systems

作者： R. Bundgen W. Kuchlin W. Lauterbach W. Schickard Institute for Informatics Universität Tubingen Tubingen Germany

We present a new gate-level hardware verification method based on term rewriting systems. As an application, we formally verify the Sparrow microprocessor with the term rewriting theorem prover ReDuX. Our designs are given as net-lists in BLIF format. We mechanically compile the net-lists into the formal axiomatization of Sparrow as a term rewriting system. ReDuX can then emulate Sparrow symbolically. We manually produce verification conditions from the user-level processor specification and verify each one of them. Our axiomatization corresponds directly to net-lists, and thus is intuitive and close to the hardware. Except for simple equations no higher concept of logic is involved.

关键词： Hardware Equations Logic design field programmable gate arrays Design optimization Silicon Informatics Microprocessors Linear discriminant analysis Plugs

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Classifying Computations on Multi-Tenant FPGAs 21

Classifying Computations on Multi-Tenant FPGAs

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Mustafa Gobulukoglu Colin Drewes Bill Hunter Dustin Richmond Ryan Kastner University of California San Diego San Diego CA USA Georgia Tech Research Institute Atlanta GA USA University of Washington Seattle WA USA

ISBN: (纸本)9781450382182

Modern data centers leverage large FPGAs to provide low latency, high throughput, and low energy computation. FPGA multi-tenancy is an attractive option to maximize utilization, yet it opens the door to unique security threats. In this work, we develop a remote classification pipeline that targets the confidentiality of multi-tenant cloud FPGA environments. We design a unique Dual-Edged voltage fluctuation sensor that measures subtle changes in the power distribution network caused by co-located computations. The sensor measurements are given to a classification pipeline that is able to deduce information about co-located applications including the type of computation and its implementation. We study the importance of the trace length, signal conditioning algorithms, and other aspects that affect classification accuracy. Our results show that we can determine if another co-tenant is present with 96% accuracy. We can classify with 98% accuracy whether a power waster circuit is operating. Furthermore, we are able to determine if a cryptographic operation is occurring, differentiate between different cryptographic algorithms (AES and PRESENT) and microarchitectural implementations (Microblaze, ORCA, and PicoRV32).

关键词： programmable logic sensor hardware security power distribution network side-channel analysis neural network multi-tenant FPGA

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Power estimation tool for system on programmable chip based platforms (abstract only) 14

Power estimation tool for system on programmable chip based ...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Santhosh Kumar Rethinagiri Oscar Palomar Adrian Cristal Osman Unsal BSC - Microsoft Research Center Barcelona Spain BSC - Mircrosoft Research Center Barcelona Spain

ISBN: (纸本)9781450326711

The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core *** effectiveness of our proposed tool is validated through dualcore RISC processor designed around the FPGA board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other

关键词： power/energy estimation fpga systemc heterogeneous architecture asic tlm speedup multicore functional power models design space exploration virtual platform accuracy

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MLBlocks: FPGA Blocks for Machine Learning Applications 21

MLBlocks: FPGA Blocks for Machine Learning Applications

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Seyedramin Rasoulinezhad David Boland Philip H.W. Leong The University of Sydney Sydney Australia

ISBN: (纸本)9781450382182

The underlying goal of FPGA architecture research is to devise flexible substrates which implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing and image processing applications through high precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: 1) higher computational density and 2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem formulation involving computing nested loops over multiply-accumulate (MAC) operations, which covers many basic linear algebra primitives and standard deep neural network (DNN) layers. A quantitative methodology for deriving efficient coarse-grained compute block architectures from benchmarks is then proposed together with a family of new compute units, called MLBlocks. These blocks are flexible mesh-based systolic array units parameterized with different data movements, data reuse, and multi-precision support. They utilize a columnar arrangement which is compatible with existing FPGA architectures. Finally, using synthetic benchmarks, we demonstrate that MLBlocks offer significantly improved performance over the commercial Xilinx DSP48E2, while maintaining similar area and timing requirements to current DSPs.

关键词： FPGA architectures reconfigurable architecture neural networks digital signal processing systolic arrays coarse-grained compute blocks

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Layout-driven detection of bridge faults in interconnects

Layout-driven detection of bridge faults in interconnects

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IEEE international symposium on Defect and Fault Tolerance in VLSI Systems

作者： Tong Liu Xiaotao Chen F. Lombardi J. Salinas Actel Corporation Sunnyvale CA USA Department of Computer Science Texas A and M University College Station TX USA Nuwc New London CT USA

This paper presents a new approach to fault detection of interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults by a novel weighted graph approach. This graph is then analyzed to appropriately schedule the order of test compaction and execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weights of the new adjacency graph as figure of merit. The advantage of the proposed approach is that on average, early detection of faults is possible using a number of tests significantly smaller than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still requiring a small number of vectors.

关键词： Fault detection Integrated circuit interconnections Circuit faults Circuit testing field programmable gate arrays Bridge circuits Character generation Computer science Processor scheduling Data mining

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KITE: a behavioural approach to fault-tolerance in FPGA-based systems

KITE: a behavioural approach to fault-tolerance in FPGA-base...

引用

IEEE international symposium on Defect and Fault Tolerance in VLSI Systems

作者： G.A. Mojoli D. Salvi M.G. Sami G.R. Sechi R. Stefanelli Diparthento di Fisica Università degli studi di Milano Milano Italy Dipaimento di Elettronica e Informazione Politecnico di Milano Milano Italy Istituto di Fisica Cosmica e Tecnologie Relative CNR Milano Italy

An approach to fault-tolerance in FPGAs is presented, based on multiple modular redundancy techniques that allows the designer to make full use of conventional CAD tools, avoiding low-level mapping problems and choosing-for the functions to which the approach is applied-the level of granularity best suited to the individual application. The single-fault model is considered insufficient, in view of experience gathered: thus the technique adopted allows one to detect up to two initial faults or to recover from up to two faults appearing sequentially in time. The structure proposed for the arbiter subsystem allows one to detect a large number of faults appearing in the arbiter as well; probability of faults appearing in the hard-core section is evaluated.

关键词： Fault tolerant systems Fault tolerance field programmable gate arrays Runtime Fault diagnosis Fault detection Multiprocessor interconnection networks Manufacturing Functional programming Read only memory

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Planarity in ROMDDs of multiple-valued symmetric functions

Planarity in ROMDDs of multiple-valued symmetric functions

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international symposium on Multiple-Valued Logic

作者： J.T. Butler J.L. Nowlin T. Sasao Department of Electrical and Computer Engineering Yaval Postgraduate School Monterrey CA USA Department of Computer Science and Electronics Kvushu Institute of Technology Iizuka Japan

We show that a multiple-valued symmetric function has a planar ROMDD (reduced ordered multiple-valued decision diagram) if and only if it is a pseudo-voting function. We show that the number of such functions is (r-1)(n+r, n+1) where r is the number of logic values and n is the number of variables. It follows from this that the fraction of symmetric multiple-valued functions that have planar ROMDDs approaches 0 as n approaches infinity. Further, we show that the worst case and average number of nodes in planar ROMDDs of symmetric functions is n/sup 2/(1/2-1/2r) and n/sup 2/(1/2-1/(r+1)), respectively, when n is large.

关键词： Data structures Boolean functions Delay Integrated circuit interconnections Merging Voting Logic functions Very large scale integration field programmable gate arrays Logic design

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