Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an ...
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ISBN:
(纸本)9781605584102
Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables- specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial FPGA architecture. Copyright 2009 acm.
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limite...
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ISBN:
(纸本)9781605584102
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limited regular expression support for wildcard patterns used by rules that represent polymorphic viruses. To reduce the amount of state needed to track so many regular expressions, PERG-Rx employs a lossy scheme which increases the rate of false positives detected as the required state grows. The scalability and dynamic updatability of the PERG-Rx architecture to database updates are also evaluated. Copyright 2009 acm.
A methodology is presented for production-time testing of segmented channel fieldprogrammablegatearrays (FPGA). The principles of this methodology are based on configuring the uncommitted modules of the FPGA as a s...
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ISBN:
(纸本)9780897917438
A methodology is presented for production-time testing of segmented channel fieldprogrammablegatearrays (FPGA). The principles of this methodology are based on configuring the uncommitted modules of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILA). These arrays are tested by establishing appropriate conditions such as constant testability. A design approach is then proposed. This approach is based on adding a small circuitry between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. Features such number of test vectors and hardware requirements are also analyzed.
An algorithm is presented for partitioning a design in time. The algorithm divides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. These configurations are rapidly executed i...
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ISBN:
(纸本)9780897919784
An algorithm is presented for partitioning a design in time. The algorithm divides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. These configurations are rapidly executed in the FPGA to emulate the large design. The tool includes facilities for optimizing the partitioning to improve routability, for fitting the design into more configurations than the depth of the critical path and for compressing the critical path of the design into fewer configurations, both to fit the design into the device and to improve performance. Scheduling results are shown for mapping designs into an 8-configuration time-multiplexed FPGA and for architecture investigation for a time-multiplexed FPGA.
In this paper we present an implementation of a Cholesky decomposition core, with IEEE754 single precision arithmetic. The datapaths are generated using fused datapath synthesis, created with an experimental floating ...
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ISBN:
(纸本)9781605584102
In this paper we present an implementation of a Cholesky decomposition core, with IEEE754 single precision arithmetic. The datapaths are generated using fused datapath synthesis, created with an experimental floating point compiler tool, capable of fitting hundreds of floating point operators into a single device. We present a scalable architecture for both real and complex matrixes, on which we will report results for up to 128128 real matrices. The concepts of fused datapath synthesis for FPGA floating point designs will be reviewed, and the application to the Cholesky algorithm detailed. Experimental results will be given to show that the accuracy of this method is superior to those expected from a traditional IEEE754 core based design flow. Copyright 2009 acm.
Since the inception of FPGAs over 2 decades ago, the micro-architectures and macro-architectures of FPGAs across all FPGA vendors have been converging strongly to the point that comparable FPGAs from the main FPGA ven...
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ISBN:
(纸本)9781450370998
Since the inception of FPGAs over 2 decades ago, the micro-architectures and macro-architectures of FPGAs across all FPGA vendors have been converging strongly to the point that comparable FPGAs from the main FPGA vendors had virtually the same use models, and the same programming models. User designs were getting easier to port from one vendor to the other with every generation. Recent developments in from different FPGA vendors targeting the most advanced semiconductor technology nodes are an abrupt and disruptive break from this trend, especially at the macro-architectural level.
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmablegatearrays (FPGAs). In this paper, we use the negotiation-based paradigm to pa...
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Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmablegatearrays (FPGAs). In this paper, we use the negotiation-based paradigm to parallelize placement. Our new FPGA placer, NAP (Negotiated Analytical Placement), uses an analytical technique for coarse placement and the negotiation paradigm for detailed placement. We describe the serial algorithm and report results. We also report findings related to parallelizing NAP under a multicast networking and multi-threaded operating system environment;the parallel placer is tolerant to multicast packet loss as well as out-of-order packet delivery. Our parallel placer exhibits little performance degradation while attaining speedups of 2 using 3 processors.
Three factors are driving the demand for rapid fieldprogrammablegate array (FPGA) compilation. First, as FPGAs grown in logic capacity, the compile computation grows more quickly than the compute power of the availa...
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Three factors are driving the demand for rapid fieldprogrammablegate array (FPGA) compilation. First, as FPGAs grown in logic capacity, the compile computation grows more quickly than the compute power of the available computers. Second, there exists a subset of users who are willing to pay for very high speed compile with a decrease in quality of result. Third, very high speed compile is a long-standing desire of those using FPGA-based custom computing machines, as they want compile times at least closer to those of regular computers. A routing algorithm and routing tool that relates these three unique capabilities to very high-speed compile is presented.
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the power of reconfigurable systems, it is im...
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ISBN:
(纸本)9780897919784
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper we propose one technique for significantly reducing the reconfiguration latency: the prefetching of configurations. By loading a configuration into the reconfigurable logic in advance of when it is needed, we can overlap the reconfiguration with useful computation. We demonstrate the power of this technique, and propose an algorithm for automatically adding prefetch operations into reconfigurable applications. This results in a significant decrease in the reconfiguration overhead for these applications.
The FPGA architectural issue of the effect of logic block functionality on FPGA performance and density is investigated. In particular, in the context of lookup tables (LUT), cluster-based island-style FPGAs, the effe...
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The FPGA architectural issue of the effect of logic block functionality on FPGA performance and density is investigated. In particular, in the context of lookup tables (LUT), cluster-based island-style FPGAs, the effect of LUT size and cluster size on the speed and logic density of an FPGA is analyzed. A fully timing-driven experimental flow, in which a set of benchmark circuits are synthesized, is used into different cluster based logic book architectures, which contain groups of LUTs and flip-flops.
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