检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

599 篇 会议
30 篇 期刊文献

馆藏范围

629 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

511 篇 工学
- 469 篇 计算机科学与技术...
- 285 篇 软件工程
- 225 篇 电子科学与技术（可...
- 144 篇 电气工程
- 88 篇 信息与通信工程
- 35 篇 动力工程及工程热...
- 35 篇 控制科学与工程
- 26 篇 机械工程
- 15 篇 生物工程
- 13 篇 仪器科学与技术
- 9 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 材料科学与工程（可...
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 3 篇 农业工程
203 篇 理学
- 170 篇 数学
- 35 篇 物理学
- 19 篇 统计学（可授理学、...
- 16 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
54 篇 管理学
- 46 篇 管理科学与工程(可...
- 29 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学

主题

275 篇 field programmab...
172 篇 field programmab...
35 篇 signal processin...
35 篇 clocks
33 篇 modulation
33 篇 ofdm
33 篇 estimation
33 篇 filtration
30 篇 fpga
9 篇 table lookup
9 篇 routing
9 篇 systolic arrays
9 篇 switches
8 篇 field-programmab...
7 篇 fpgas
7 篇 optimization
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university
3 篇 state key lab of...
3 篇 computer science...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

622 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 629 条记录，以下是81-90 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An FPGA generator for multipoint distributed random variables

An FPGA generator for multipoint distributed random variable...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Liberati, Nicola Bruti Platen, Eckhard Martini, Filippo Piccardi, Massimo School of Finance and Economics Department of Mathematical Sciences University of Technology Sydney Australia Faculty of Information Technology University of Technology Sydney Australia

Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differential equations. In applications such as finance, where "real time" execution is required, there is a strong need for highly efficient implementations. In this paper a fast and flexible dedicated hardware solution on a field programmable gate Array (FPGA) is presented. A comparative performance analysis between a software-only and the proposed hardware solution demonstrates that the FPGA solution is bottleneck-free, retains the flexibility of the software solution and significantly increases the computational efficiency.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Fast integrated tools for circuit design with FPGAs 98

Fast integrated tools for circuit design with FPGAs

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Gehring, Stephan W. Ludwig, Stefan H.-M. Zurich Switzerland

ISBN: (纸本)9780897919784

To implement high-density and high-speed FPGA circuits, designers need tight control over the circuit implementation process. However, current design tools are unsuited for this purpose as they lack fast turnaround times, interactiveness, and integration. We present a system for the Xilinx XC6200 FPGA, which addresses these issues. It consists of a suite of tightly integrated tools for the XC6200 architecture centered around an architecture-independent tool framework. The system lets the designer easily intervene at various stages of the design process and features design cycle times (from an HDL specification to a complete layout) in the order of seconds.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

FPGA clock network architecture: Flexibility vs. area and power

FPGA clock network architecture: Flexibility vs. area and po...

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Lamoureux, Julien Wilton, Steven J. E. Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)1595932925

This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for field-programmable gate arrays (FPGA's). The paper begins by describing a parameterized clock network model that describes a broad range of programmable clock network architectures. Specifically, the model supports architectures with multiple local and global clock domains and varying amounts of flexibility at various levels of the clock network. Using the model, the architectural parameters that control the flexibility of the clock network are varied to determine the cost of this flexibility in terms of area and power dissipation. From these experiments, the study finds that area and power costs are highest for networks with flexibility close to the logic blocks. Furthermore, it found that clock networks with local clock domains have little overhead and are significantly more efficient than clock networks without local clock domains for applications with multiple clocks. Copyright 2006 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

A 2005 review of FPGA arithmetic

A 2005 review of FPGA arithmetic

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Simard, Stéphane Beguenane, Rachid Larouche, Éric Morin, Luc ERMETIS Research Group Université du Québec à Chicoutimi Chicoutimi Que. G7H 2B1 Canada Novakod Technologies Inc. 930 Jacques Cartier Est Chicoutimi Que. G7H 7K9 Canada

This article is a concise literature review of the actual state of the art in arithmetic for field-programmable gate arrays (FPGAs), including studies, implementation techniques, operators, and structures, in various area-time tradeoffs. It covers the integer operations of addition/subtraction, multiplication, squaring, division, and square root, in parallel, and in both serial modes (least-significant digit first, and online). Many people, including researchers in the field of computer arithmetic, parallel computing, digital signal and image processing, system-on-a-programmable chip (SoPC) designers, and other people with a need to implement special purpose arithmetic circuits on FPGAs, might find such a review useful, either as an introduction to the topic, as a knowledge update, or for reference.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Is marriage in the cards for programmable logic, microprocessors and ASICs?

Is marriage in the cards for programmable logic, microproces...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Anon

来源：评论

学校读者我要写书评

暂无评论

A comparison of programmable gate array logic cell circuits

A comparison of programmable gate array logic cell circuits

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Chau, Thomas C.P. Leong, H.W. Ho, Sam M.H. Chan, Brian P.W. Yuen, Steve C.L. Pun, Kong-Pang Choy, Oliver C.S. Wang, Xinan Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong Hong Kong Department of Electronic Engineering Chinese University of Hong Kong Hong Kong Hong Kong School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781605584102

Via-programmable gate arrays (VPGAs) offer a middle ground application specific integrated circuits and field programmable arrays in terms of flexibility, manufactuing , speed, power and area. In this paper, we present a VPGA logic cell, the complementary universal logic (CULG) which can be used to implement both sequential combinatorial elements. Its performance is compared a number of other designs including transmission , differential cascode voltage switch with pass gate, standard cell. The CULG is found to have comparable delay product and process variation sensitivity to the other designs while offering the lowest power consumption. Copyright 2009 acm.

关键词： Logic gates

来源：评论

学校读者我要写书评

暂无评论

Optimizations for a highly cost-efficient programmable logic architecture 98

Optimizations for a highly cost-efficient programmable logic...

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Veenstra, Kerry Pedersen, Bruce Schleicher, Jay Sung, Chiakang Altera Corp San Jose CA United States

ISBN: (纸本)9780897919784

Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. This paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.

关键词： programmable logic controllers

来源：评论

学校读者我要写书评

暂无评论

Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in FPGA devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal FPGA Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC FPGA Architecture FPGA CAD Xilinx

来源：评论

学校读者我要写书评

暂无评论

High-Performance QR Decomposition for FPGAs 18

High-Performance QR Decomposition for FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Langhammer, Martin Pasca, Bogdan Intel Programmable Solut Grp Swindon Wilts England Intel Programmable Solut Grp Paris France

ISBN: (纸本)9781450356145

QR decomposition (QRD) is of increasing importance for many current applications, such as wireless and radar. Data dependencies in known algorithms and approaches, combined with the data access patterns used in many of these methods, restrict the achievable performance in software programmable targets. Some FPGA architectures now incorporate hard floating-point (HFP) resources, and in combination with distributed memories, as well as the flexibility of internal connectivity, can support high-performance matrix arithmetic. In this work, we present the mapping to parallel structures with inter-vector connectivity of a new QRD algorithm. Based on a Modified Gram-Schmidt (MGS) algorithm, this new algorithm has a different loop organization, but the dependent functional sequences are unchanged, so error analysis and numerical stability are unaffected. This work has a theoretical sustained-to-peak performance close to 100% for large matrices, which is roughly three times the functional density of the previously best known implementations. Mapped to an Intel Arria 10 device, we achieve 80us for a 256x256 single precision real matrix, for a 417 GFLOP equivalent. This corresponds to a 95% sustained to peak ratio, for the portion of the device used for this work.

关键词： QRD MGS FPGA Arria10 throughput

来源：评论

学校读者我要写书评

暂无评论

Quantifying the cost and benefit of latency insensitive communication on FPGAs 14

Quantifying the cost and benefit of latency insensitive comm...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Murray, Kevin E. Betz, Vaughn Dept. of Electrical and Computer Engineering University of Toronto Ontario Canada

ISBN: (纸本)9781450326711

Latency insensitive communication oers many potential benets for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共63页 << < 5 6 7 8 9 10 11 12 13 14 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：