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24th International conference on Information Integration and Web Intelligence, iiWAS 2022, held in conjunction with the 20th International conference on advances in Mobile computing and Multimedia Intelligence, MoMM 2022

24th International Conference on Information Integration and...

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24th International conference on Information Integration and Web Intelligence, iiWAS 2022, held in conjunction with the 20th International conference on advances in Mobile computing and Multimedia Intelligence, MoMM 2022

ISBN: (纸本)9783031210464

The proceedings contain 53 papers. The special focus in this conference is on Information Integration and Web Intelligence. The topics include: GPU Accelerated parallel Implementation of Linear Programming Algorithms;Towards Explaining DL Non-entailments by Utilizing Subtree Isomorphisms;Query Optimization in NoSQL Databases Using an Enhanced Localized R-tree Index;handling Exit Node Vulnerability in Onion Routing with a Zero-Knowledge Proof;an Accurate, Flexible and Private Trajectory-Based Contact Tracing System on Untrusted Servers;bilateral Bargaining for Healthcare Data Sharing;modifying Neo4j’s Object Graph Mapper Queries for Access Control;a Recommendation Method for Recipes Containing Unskillful Elements Using Naïve Bayes Classifier to Improve Cooking Skills;extraction of Complementary Topics Based on Phrase Importance and Co-occurrence in Technical Blogs;sharing Semantic Knowledge for Autonomous Robots: Cooperation for Social Robotic Systems;feature Relevance Analysis of Product Reviews to Support Online Shopping;annotation System for Dialogue Datasets of Older Adult’s with Photos and Storytelling;evaluation Axes for Automatically Generated Product Descriptions;CISQA: Corporate Smart Insights Question Answering System;symmetry Metrics for Pairwise Entity Similarities;a New Method to Measure Similarity of Words in Japanese Twitter Based on Related Images;Hybrid Phishing URL Detection Using Segmented Word Embedding;a Scheme for News Article Classification in a Low-Resource Language;expertise Computation for Automatic Reviewer Assignment;detection of Hot Topics Using Multi-view Text Clustering;exploiting Named Entity Recognition for Information Extraction from Italian Procurement Documents: A Case Study;interactive Visualization of Comic Character Correlation Diagrams for Understanding Character Relationships and Personalities;two Case Studies on Guiding Human Behavior Using Virtualization Technologies in distributed Virtual Shopping Malls;central Figures in t

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Integer sorting algorithms for coarse-grained parallel machines

Integer sorting algorithms for coarse-grained parallel machi...

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International conference on High Performance computing

作者： K. Alsabti S. Ranka School of CIS Syracuse University USA Department of CISE University of Florida USA

Integer sorting is a subclass of the sorting problem where the elements have integer values and the largest element is polynomially bounded in the number of elements to be sorted. It is useful for applications in which the size of the maximum value of element to be sorted is bounded. In this paper, we present a new distributed radix-sort algorithm for integer sorting. The structure of our algorithm is similar to radix sort except that it typically requires less number of communication phases. We present experimental results for our algorithm on two distributed memory multiprocessors, the Intel Paragon and the Thinking machine CM-5. These results are compared with two other well known practical parallel sorting algorithms based on radix sort and sample sort. The experimental results show that the distributed radix-sort is competitive with the other two algorithms.

关键词： Sorting parallel machines Polynomials Costs User-generated content Multiprocessor interconnection networks Hypercubes Computational Intelligence Society Contracts Subcontracting

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High performance mainframe computer cables

High performance mainframe computer cables

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47th Electronic Components and Technology conference (ECTC)

作者： Beaman, B Component Engineering IBM World Wide Procurement NC USA

ISBN: (纸本)078033857X;0780338588

The mainframe computer is a fascinating combination of various packaging technologies including multichip modules, card-on-board assemblies, DC-DC power supplies, and high performance cable assemblies. advances in chip technology along with higher density first and second level packaging have reduced the number of cables used in mainframe computers while the performance requirements for cables have continued to increase. High performance mainframe cables have evolved over the years from simple transmission line ribbon cables to custom discrete mini-coax cables. The latest evolutionary change is a spin-off from the standard SCSI style cable referred to as the Sn cable. The STI (self timed interface) cable is a hybrid 'SCSI style' cable used in the latest IBM S/390 mainframes. The STI cables use standard 50 pin SCSI connector hardware and a 22 pair bulk wire to provide up to 330 Mb/s data transfer rates for each of the differential pairs in the cable. The cables are used for both internal and external connections between processors and provide 8 bit data in and data out paths as well as parity and clock signals. Although a key feature of the STI interface is the ability to compensate for pair-to-pair skew variations, the signal skew within a pair must be very low to be able to support cable assembly lengths up to 20 meters. The SCSI connector interface has several features that make it well suited for use as a high performance cable including good EMI shielding, high contact density, and numerous card mounting styles and cable assembly options. Various bulk wire alternates have been evaluated to determine the optimum combination of cable performance, physical size (wire diameter), and cost per unit length. These cable alternatives include a standard shielded twisted pair cable, a 3M(**) pleated foil ribbon cable, a GORE(**) QUAD(**) cable, and an Amphenol(**) Spectra-Strip(**) parallel pair cable. An unconventional wire termination technique is used in the STI cable a

关键词： High performance computing Cables Packaging Assembly Multichip modules Power supplies Power transmission lines Connectors Hardware Wire

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A new parallel matrix multiplication algorithm on distributed-memory concurrent computers

A new parallel matrix multiplication algorithm on distribute...

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International conference on High Performance computing in the Asia-Pacific Region

作者： Jaeyoung Choi School of Computing Soongsil University Seoul South Korea

The author presents a new parallel matrix multiplication algorithm on distributed memory concurrent computers, which is fast and scalable, and whose performance is independent of data distribution on processors, and calls it DIMMA (Distribution-Independent Matrix Multiplication Algorithm). The algorithm is based on two new ideas; it uses a modified pipelined communication scheme to overlap computation and communication effectively and exploits the LCM block concept to obtain the maximum performance of the sequential BLAS routine in each processor even when the block size is very small as well as very large. The algorithm is implemented and compared with SUMMA on the Intel Paragon computer.

关键词： Concurrent computing distributed computing Jacobian matrices Broadcasting Grid computing Wrapping Linear algebra Design optimization

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Bottleneck-free interconnect and IO subsystem in SPAX

Bottleneck-free interconnect and IO subsystem in SPAX

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International conference on parallel and distributed Systems (ICPADS)

作者： Kangwoo Lee Woo-Jong Han M. Dubois Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA Electronics and Telecommunications Research Institute Daejeon South Korea

The performance of parallel systems under commercial applications strongly depend on the speeds of IO subsystems and interconnects. Any single bottleneck in there hinder one from fully taking advantages of today's faster CPUs and better instruction architectures. Therefore, configuring bottleneck-free IO subsystems and interconnects is essential. In this paper we considered IO subsystem and interconnect in SPAX system. When the SPAX's IO subsystem is lightly equipped, the first bottleneck appears at disk drives. Although the disk bottleneck can be removed by putting more disks, another bottleneck was detected at the data buffer which is the first component in communication path. That is to say, all components in IO subsystems and interconnects must be sufficiently equipped, simultaneously, to thoroughly eliminate the bottleneck. We could reach a cost-effective bottleneck-free configuration of SPAX by making use of its flexible hardware design. The simulation results of SPAX then show significant performance gain from faster CPUs with better instruction architectures.

关键词： Hardware Benchmark testing Neck Disk drives Computer aided instruction parallel architectures Scientific computing Concurrent computing Electronic equipment testing Computer buffers

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Run-time parallelization for partially parallel loops

Run-time parallelization for partially parallel loops

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International conference on parallel and distributed Systems (ICPADS)

作者： Chao-Tung Yang Shian-Shyong Tseng Shih Hung Kao Ming-Hui Hsieh Mon-Fong Jiang ROCSAT Ground Segment National Space Program Office Hsinchu Taiwan Department Computer & Information Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)0818682272

In this paper, a run-time technique based on inspector-executor scheme is proposed to find available parallelism on loops in this paper. Our inspector can determine the wavefronts by building a DEF-USE table. Additionally, the process of inspector for finding the wavefronts, can be parallelized fully without any synchronization. Our executor can perform the loop iterations concurrently. For each wavefront in a loop, the auto-adapted function is used to get a tailored thread number rather than using fixed thread number for execution. Experimental results show that our new parallel inspector can handle complex data dependency patterns and reduce itself execution time obviously. Besides, the new partitioning strategy for executor can also improve the performance of run-time parallelization obviously.

关键词： Runtime parallel processing Yarn Data analysis Chaos Concurrent computing Processor scheduling Sparse matrices Data mining Helium

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Integrating concurrency control and distributed data into workflow frameworks: an actor model perspective

Integrating concurrency control and distributed data into wo...

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IEEE International conference on Systems, Man and Cybernetics

作者： A. Esposito V. Loia Dipartimento di Matematica e Infomatica Università di Salemo Baronissi Salerno Italy

Technological advances in processor power, networking, telecommunications and multimedia are stimulating the development of applications requiring parallel and distributed computing. This new perspective is enticing research into new design methodologies that view the software as an "intelligent" collection of agents that interact by coordinating knowledge-based processes. We present an actor-based workflow architecture that would fit naturally into distributed heterogeneous environments. The actors combine object-oriented and functional programming in order to make the management of concurrency easier for the user.

关键词： Concurrency control Object oriented modeling distributed computing Concurrent computing Message passing Multimedia computing Design methodology Computer architecture Functional programming Artificial intelligence

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Mapping nested loops onto distributed memory multiprocessors

Mapping nested loops onto distributed memory multiprocessors

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International conference on parallel and distributed Systems (ICPADS)

作者： N. Koziris G. Papakonstantinou P. Tsanakas Department of Electrical and Computer Engineering Computer Science Division National and Technical University of Athens Zografou Greece

The paper presents Chain grouping; a new low complexity method for the problem of partitioning the index space into groups with little intercommunication requirements, for mapping onto distributed mesh connected architectures. First the loop iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the index space is divided into discrete groups of related computations, which are assigned to different processors, while preserving the optimal makespan. The Chain grouping method is based on grouping along a uniform chain of computations, formed by a particular dependence vector. This vector will be proved as the best to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved, and the references to intragroup computations are considerably increased. The partitioned groups are afterwards assigned to meshes of processors. The resulting space mapping maximises processor utilisation and cuts down overall communication delays while preserving the optimal hyperplane time schedule.

关键词： Processor scheduling Concurrent computing Vectors Computer architecture parallel architectures Delay effects Systolic arrays parallel processing Computer science Scheduling algorithm

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Analysis of heat and fluid flow in a PCB channel using KAICUBE/Hanbit-1 parallel computer

Proceedings of the Conference on High Performance Computing ...

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proceedings of the conference on High Performance computing on the Information Superhighway, HPC Asia'97 1997年 89-92页

作者： Yun, B.T. Choi, D.H. Korea Advanced Inst of Science and Technology Taejon Korea Republic of

A three-dimensional analysis code for mixed convection flow through the printed-circuit-board (PCB) channel on which heat generating chip modules are mounted has been developed. For uniformly distributed modules, a small domain containing single module is considered with periodic and symmetry boundary conditions. Calculations have been made for various Grashof numbers to examine the effects of natural convection for both adiabatic and conducting wall conditions. The program is designed to run on the KAICUBE/Hanbit-1 parallel computer and its performance on different machines is compared in the paper.

关键词： Printed circuit boards

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Task scheduling in distributed computing systems with a genetic algorithm

Task scheduling in distributed computing systems with a gene...

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International conference on High Performance computing in the Asia-Pacific Region

作者： Sung-Ho Woo Sung-Bong Yang Shin-Dug Kim Tack-Don Han Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

Scheduling a directed acyclic graph (DAG) which represents the precedence relations of the tasks of a parallel program in a distributed computing system (DCS) is known as an NP-complete problem except for some special cases. Many heuristic-based methods have been proposed under various models and assumptions. A DCS can be classified in two types according to the characteristics of the processors on a network: a distributed homogeneous system (DHOS) and a distributed heterogeneous system (DHES). The paper defines a general model for a DHOS and a DHES and presents a genetic algorithm (GA) to solve the task scheduling problem in the defined DCS. The performance of the proposed GA is compared with the list scheduling algorithm in a DHOS and with the one-level reach-out greedy algorithm (OLROG) in a DHES. The proposed GA has shown better performance in various environments than other scheduling methods.

关键词： Processor scheduling distributed computing Genetic algorithms distributed control Scheduling algorithm Job shop scheduling Data communication Robustness parallel processing Laboratories

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