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Collaboration and visual steering of simulations

Collaboration and visual steering of simulations

引用

conference on Visual Data Exploration and Analysis IV

作者： Zou, S Ribarsky, W Jean, Y Heiner, J Schwan, K Sumner, B Okuma, O Georgia Institute of Technology (United States) Lucent Technologies Bell Labs. (United States)

ISBN: (纸本)0819424285

This paper presents a structure and set of tools to address the needs of groups of scientists working on large, time-dependent simulations. It describes a direct manipulation, 3D steering environment that is integrated with a controller for instrumenting parallel computations, collecting output, and passing it in binary made between heterogeneous machines, The instrumentation allows collection of data at chosen points in the model and control of the computation through changes of parameters or insertion of alternate data. The steering interface and controller are joined with a library of collaborative communication tools, With these tools a user may steer a simulation and share both the steering input and visual output with one or several colleagues, The tools permit the trading of steering and visualization tools within the group. In addition a lime-dependent steering interface has been introduced. Here time is treated on exactly the same basis as the spatial dimensions so there is a 4D environment, 3 shown spatially and one through animation. The steering interface is built upon a flexible visualization/analysis system. This permits the immediate display of time-dependent results from the dynamic simulations and refined interaction with the results to bring out the character and correlations of multivariate data. The user can then launch new simulations at any stage in this exploration using the visualization to define and focus the simulation parameters, region of interest, and time frame.

关键词： computational steering computer simulation visualization collaboration collaborative work distributed computing 3D graphical interface

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Adaptive multivariate integration using MPI

Adaptive multivariate integration using MPI

引用

International conference on High Performance computing

作者： E. de Doncker A. Gupta M. Guo Department of Computer Science Western Michigan University Kalamazoo MI USA

We describe a coarse grain parallel algorithm for multivariate adaptive integration using MPI. The algorithm is asynchronous in nature and allows for load balancing. Timing results show good speedups obtained on a net... 详细信息

关键词： Load management Workstations Algorithm design and analysis parallel algorithms Bayesian methods Computer science Timing Statistical analysis Statistical distributions distributed algorithms

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Universally fault-tolerant broadcasting in trees

Universally fault-tolerant broadcasting in trees

引用

International conference on parallel and distributed Systems (ICPADS)

作者： P. Panaite A. Pelc Department d' Informatique Universite du Quebec a Hull Hull QUE Canada

We consider broadcasting a message from one node of a tree to all other nodes. In the presence of up to k link failures the tree becomes disconnected, and only nodes in the connected component C containing the source can be informed. The maximum ratio between the time used by a broadcasting scheme B to inform C and the optimal time to inform C, taken over all components C yielded by configurations of at most k faults, is the k-vulnerability of B. This is the maximum slowdown incurred by B due to the lack of a priori knowledge of fault location, for at most k faults. Since the upper bound k on the number of faults is not always known, it is important to design broadcasting schemes that behave well under any possible number of faults. It turns out that achieving the lowest possible k-vulnerability for all k simultaneously is impossible for some trees. Hence a natural goal is to seek, for any tree T, a broadcasting scheme that simultaneously approximates the lowest possible k-vulnerability for every k, up to a given constant factor c (independent of L). We describe a polynomial algorithm which decides if such a "universally fault-tolerant" broadcasting scheme exists for given T and c, and constructs such a scheme if it exists.

关键词： Fault tolerance Broadcasting Upper bound distributed computing Communication networks Fault location Polynomials Casting distributed databases Concurrent computing

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Mapping of finite-element grids onto parallel computers using neural networks

Mapping of finite-element grids onto parallel computers usin...

引用

IEEE International conference on Algorithms and Architectures for parallel Processing (ICAP)

作者： R.S. Tan V. Lakshmi Narasimhan Department of Electrical Engineering University of Queensland QLD Australia Department of Computer Science University of South Australia SA Australia Defence Science and Technology Organisation SA Australia

In this paper, LSOM (Load-balancing Self-Organizing Map), a neural network based on Kohonen's self-organizing map is proposed for the problem of mapping finite-element method (FEM) grids to distributed-memory parallel computers with mesh interconnection networks. The rough global ordering produced by LSOM is then combined with the local refinement Kernighan-Lin algorithm (called LSOM-KL) to obtain the solution. LSOM-KL obtained a load imbalance of less than 0.1% and a low number of hops, comparable to results obtained with commonly used recursive bisection methods.

关键词： Finite element methods Computer networks Concurrent computing Grid computing Neural networks distributed computing Load management Network topology Computer network reliability Multiprocessor interconnection networks

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High performance mainframe computer cables

High performance mainframe computer cables

引用

47th Electronic Components and Technology conference (ECTC)

作者： Beaman, B Component Engineering IBM World Wide Procurement NC USA

ISBN: (纸本)078033857X;0780338588

The mainframe computer is a fascinating combination of various packaging technologies including multichip modules, card-on-board assemblies, DC-DC power supplies, and high performance cable assemblies. advances in chip technology along with higher density first and second level packaging have reduced the number of cables used in mainframe computers while the performance requirements for cables have continued to increase. High performance mainframe cables have evolved over the years from simple transmission line ribbon cables to custom discrete mini-coax cables. The latest evolutionary change is a spin-off from the standard SCSI style cable referred to as the Sn cable. The STI (self timed interface) cable is a hybrid 'SCSI style' cable used in the latest IBM S/390 mainframes. The STI cables use standard 50 pin SCSI connector hardware and a 22 pair bulk wire to provide up to 330 Mb/s data transfer rates for each of the differential pairs in the cable. The cables are used for both internal and external connections between processors and provide 8 bit data in and data out paths as well as parity and clock signals. Although a key feature of the STI interface is the ability to compensate for pair-to-pair skew variations, the signal skew within a pair must be very low to be able to support cable assembly lengths up to 20 meters. The SCSI connector interface has several features that make it well suited for use as a high performance cable including good EMI shielding, high contact density, and numerous card mounting styles and cable assembly options. Various bulk wire alternates have been evaluated to determine the optimum combination of cable performance, physical size (wire diameter), and cost per unit length. These cable alternatives include a standard shielded twisted pair cable, a 3M(**) pleated foil ribbon cable, a GORE(**) QUAD(**) cable, and an Amphenol(**) Spectra-Strip(**) parallel pair cable. An unconventional wire termination technique is used in the STI cable a

关键词： High performance computing Cables Packaging Assembly Multichip modules Power supplies Power transmission lines Connectors Hardware Wire

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Integer sorting algorithms for coarse-grained parallel machines

Integer sorting algorithms for coarse-grained parallel machi...

引用

International conference on High Performance computing

作者： K. Alsabti S. Ranka School of CIS Syracuse University USA Department of CISE University of Florida USA

Integer sorting is a subclass of the sorting problem where the elements have integer values and the largest element is polynomially bounded in the number of elements to be sorted. It is useful for applications in which the size of the maximum value of element to be sorted is bounded. In this paper, we present a new distributed radix-sort algorithm for integer sorting. The structure of our algorithm is similar to radix sort except that it typically requires less number of communication phases. We present experimental results for our algorithm on two distributed memory multiprocessors, the Intel Paragon and the Thinking machine CM-5. These results are compared with two other well known practical parallel sorting algorithms based on radix sort and sample sort. The experimental results show that the distributed radix-sort is competitive with the other two algorithms.

关键词： Sorting parallel machines Polynomials Costs User-generated content Multiprocessor interconnection networks Hypercubes Computational Intelligence Society Contracts Subcontracting

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A new parallel matrix multiplication algorithm on distributed-memory concurrent computers

A new parallel matrix multiplication algorithm on distribute...

引用

International conference on High Performance computing in the Asia-Pacific Region

作者： Jaeyoung Choi School of Computing Soongsil University Seoul South Korea

The author presents a new parallel matrix multiplication algorithm on distributed memory concurrent computers, which is fast and scalable, and whose performance is independent of data distribution on processors, and calls it DIMMA (Distribution-Independent Matrix Multiplication Algorithm). The algorithm is based on two new ideas; it uses a modified pipelined communication scheme to overlap computation and communication effectively and exploits the LCM block concept to obtain the maximum performance of the sequential BLAS routine in each processor even when the block size is very small as well as very large. The algorithm is implemented and compared with SUMMA on the Intel Paragon computer.

关键词： Concurrent computing distributed computing Jacobian matrices Broadcasting Grid computing Wrapping Linear algebra Design optimization

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Bottleneck-free interconnect and IO subsystem in SPAX

Bottleneck-free interconnect and IO subsystem in SPAX

引用

International conference on parallel and distributed Systems (ICPADS)

作者： Kangwoo Lee Woo-Jong Han M. Dubois Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA Electronics and Telecommunications Research Institute Daejeon South Korea

The performance of parallel systems under commercial applications strongly depend on the speeds of IO subsystems and interconnects. Any single bottleneck in there hinder one from fully taking advantages of today's faster CPUs and better instruction architectures. Therefore, configuring bottleneck-free IO subsystems and interconnects is essential. In this paper we considered IO subsystem and interconnect in SPAX system. When the SPAX's IO subsystem is lightly equipped, the first bottleneck appears at disk drives. Although the disk bottleneck can be removed by putting more disks, another bottleneck was detected at the data buffer which is the first component in communication path. That is to say, all components in IO subsystems and interconnects must be sufficiently equipped, simultaneously, to thoroughly eliminate the bottleneck. We could reach a cost-effective bottleneck-free configuration of SPAX by making use of its flexible hardware design. The simulation results of SPAX then show significant performance gain from faster CPUs with better instruction architectures.

关键词： Hardware Benchmark testing Neck Disk drives Computer aided instruction parallel architectures Scientific computing Concurrent computing Electronic equipment testing Computer buffers

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Run-time parallelization for partially parallel loops

Run-time parallelization for partially parallel loops

引用

International conference on parallel and distributed Systems (ICPADS)

作者： Chao-Tung Yang Shian-Shyong Tseng Shih Hung Kao Ming-Hui Hsieh Mon-Fong Jiang ROCSAT Ground Segment National Space Program Office Hsinchu Taiwan Department Computer & Information Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)0818682272

In this paper, a run-time technique based on inspector-executor scheme is proposed to find available parallelism on loops in this paper. Our inspector can determine the wavefronts by building a DEF-USE table. Additionally, the process of inspector for finding the wavefronts, can be parallelized fully without any synchronization. Our executor can perform the loop iterations concurrently. For each wavefront in a loop, the auto-adapted function is used to get a tailored thread number rather than using fixed thread number for execution. Experimental results show that our new parallel inspector can handle complex data dependency patterns and reduce itself execution time obviously. Besides, the new partitioning strategy for executor can also improve the performance of run-time parallelization obviously.

关键词： Runtime parallel processing Yarn Data analysis Chaos Concurrent computing Processor scheduling Sparse matrices Data mining Helium

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Mapping nested loops onto distributed memory multiprocessors

Mapping nested loops onto distributed memory multiprocessors

引用

International conference on parallel and distributed Systems (ICPADS)

作者： N. Koziris G. Papakonstantinou P. Tsanakas Department of Electrical and Computer Engineering Computer Science Division National and Technical University of Athens Zografou Greece

The paper presents Chain grouping; a new low complexity method for the problem of partitioning the index space into groups with little intercommunication requirements, for mapping onto distributed mesh connected architectures. First the loop iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the index space is divided into discrete groups of related computations, which are assigned to different processors, while preserving the optimal makespan. The Chain grouping method is based on grouping along a uniform chain of computations, formed by a particular dependence vector. This vector will be proved as the best to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved, and the references to intragroup computations are considerably increased. The partitioned groups are afterwards assigned to meshes of processors. The resulting space mapping maximises processor utilisation and cuts down overall communication delays while preserving the optimal hyperplane time schedule.

关键词： Processor scheduling Concurrent computing Vectors Computer architecture parallel architectures Delay effects Systolic arrays parallel processing Computer science Scheduling algorithm

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