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Multi-modal interaction in the age of information appliances

Multi-modal interaction in the age of information appliances

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IEEE International conference on Multimedia and Expo (ICME)

作者： S.H. Maes T.V. Raman IBM Thomas J. Watson Research Center USA

The coming millennium will be characterized by the availability of multiple information appliances that make ubiquitous information access an accepted fact of life. The ability to access and transform information via a multiplicity of appliances, each designed to suit the user's specific usage environment, requires the exploitation of all available input and output modalities to maximize the band-width of man-machine communication. There will be an increasingly strong demand for devices that present the same set of functionalities when accessing and manipulating the information, independently of the access device. The resulting uniform interface must be inherently multi-modal and dialog driven. This paper addresses the challenges of coordinated, synchronized multimodal user interaction that is inherent in designing user interfaces that work across these multiplicity of information appliances. Amongst the key issues to be addressed are the user's ability to interact in parallel with the same information via a multiplicity of appliances and user interfaces, and the need to present a unified, synchronized view of information across the various appliances that the user deploys to interact with information. We achieve such synchronized interactions and views by adopting the well-known Model, View, Controller (MVC) design paradigm and adapting it to conversational interactions. The resulting conversational MVC (CMVC) is to be considered as the key underlying principle of any conversational multi-modal application.

关键词： Home appliances Man machine systems Pervasive computing User interfaces Computer networks distributed computing Telephony HTML Computer network management IP networks

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A visual computing environment for very large scale biomolecular modeling

A visual computing environment for very large scale biomolec...

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International conference on Application Specific Systems (ASAP), Architectures and Processors

作者： M. Zeller J.C. Phillips A. Dalke W. Humphrey K. Schulten R. Sharma T.S. Huang V.I. Pavlovic Y. Zhao Z. Lo S. Chu Backman Institute for Advanced Science and Technology University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

Knowledge of the complex molecular structures of living cells is being accumulated at a tremendous rate. Key technologies enabling this success have been, high performance computing and powerful molecular graphics applications, but the technology is beginning to seriously lag behind challenges posed by the size and number of new structures and by the emerging opportunities in drug design and genetic engineering. A visual computing environment is being developed which permits interactive modeling of biopolymers by linking a 3D molecular graphics program with an efficient molecular dynamics simulation program executed on remote high-performance parallel computers. The system will be ideally suited for distributed computing environments, by utilizing both local 3D graphics facilities and the peak capacity of high-performance computers for the purpose of interactive biomolecular modeling. To create an interactive 3D environment three input methods will be explored: (1) a six degree of freedom "mouse" for controlling the space shared by the model and the user; (2) voice commands monitored through a microphone and recognized by a speech recognition interface; (3) hand gestures, detected through cameras and interpreted using computer vision techniques. Controlling 3D graphics connected to real time simulations and the use of voice with suitable language semantics, as well as hand gestures, promise great benefits for many types of problem solving environments. Our focus on structural biology takes advantage of existing sophisticated software, provides concrete objectives, defines a well-posed domain of tasks and offers a well-developed vocabulary for spoken communication.

关键词： Large-scale systems Computer graphics Pharmaceutical technology Concurrent computing Computational modeling distributed computing Speech recognition High performance computing Drugs Genetic engineering

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Datarol: a parallel machine architecture for fine-grain multithreading

Datarol: a parallel machine architecture for fine-grain mult...

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Working conference on Massively parallel Programming Models

作者： M. Amamiya H. Tomiyasu S. Kusakabe Department of Intelligent Systems Kyushu University Fukuoka Japan

We discuss a design principle of massively parallel distributed-memory multiprocessor architecture which solves latency problem, and present the Datarol machine architecture. Latencies, caused by remote memory access and remote procedure call, are most serious problems in massively parallel computers. In order to eliminate the processor idle times caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes. First, we present a processor architecture, called Datarol-II, that promotes efficient fine-grain multithread execution by performing fast context switching among fine-grain concurrent processes. In the Datarol-II processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memory access overhead caused by context switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. Then, we present a cost-effective design of the Datarol-II processor, which incorporates off-the-shelf high-end microprocessor while preserving the fine-grain dataflow concept. The off-the-shelf microprocessor Pentium is used for its core processing, and a co-processor called FMP (Fine-grain Message Processor) is designed for fine grained message handling and communication controls. The co-processor FMP is designed on the basis of FMD (Fine-grain Message Driven) execution model, in which fine-grain multi-threaded execution is driven and controlled by simple fine-grain message communications.

关键词： parallel machines Computer architecture Delay Microprocessors Coprocessors Communication system control Concurrent computing Registers Pipelines Load flow control

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GriT: a CORBA-based grid middleware architecture

GriT: a CORBA-based grid middleware architecture

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Annual Hawaii International conference on System Sciences (HICSS)

作者： A.S. Gokhale B. Natarajan Institute for Software Integrated Systems Vanderbilt University Nashville TN USA

Rapid advances in networking, hardware, and middleware technologies are facilitating the development and deployment of grid applications, which are characterized, by their very high computing and resource requirements. These applications and services have multiple, simultaneous end-to-end quality of service (QoS) requirements, such as delay guarantees, jitter guarantees, security, scalability, reliability and availability guarantees, and bandwidth and throughput guarantees. Moreover, these applications and services require secure, controlled, reliable, and guaranteed access to different types of resources, such as network bandwidth, computing power, and storage capabilities, available from multiple service providers. To support next-generation grid applications effectively, there is a need to simplify grid programming by developing a new grid middleware that raises the level of abstraction, and reduces the accidental complexities incurred, by programming at the grid infrastructure middleware level offered by existing grid middleware such as Globus, ICENI, and Legion. Moreover, the new grid middleware must ensure multiple end-to-end QoS properties simultaneously. The paper provides three contributions to the research on next generation grid middleware architecture that provides the above-mentioned properties. First, we describe how we are utilizing the standards-based CORBA distributed object computing and integration technology to design the next generation grid middleware, called Grid TAO (GriT) that complements and enhances existing low-level Grid middleware, such as Globus. Second, we describe how we are using the real-time, fault-tolerant, and data parallel CORBA features to implement GriT to provide the desired properties. Finally, we show how CORBA's platform and language independence features are used in GriT to resolve the portability and interoperability challenges faced, by current grid applications.

关键词： Middleware Quality of service Computer architecture Computer networks Grid computing Bandwidth Hardware Delay Jitter Scalability

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Comparisons of fast 2D-DCT algorithms for parallel programmable digital signal processors

Comparisons of fast 2D-DCT algorithms for parallel programma...

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International conference on High Performance computing in the Asia-Pacific Region

作者： Hyuk-Jae Lee Jae-Beom Lee H. Byun Computer Science Program Louisiana Tech University Ruston LA USA Department of Electrical Engineering Columbia University New York NY USA Department of Computer Science Yonsei University Seoul South Korea

Recent advances in technology make it possible to integrate multiple processors into a single chip to build high performance parallel programmable digital signal processors (PPDSPs). These processors are expected to replace many dedicated digital signal processors to implement important image/signal processing algorithms such as discrete cosine transform (DCT). The paper addresses the issue of how to compare fast 2D-DCT algorithms when they are implemented on a PPDSP. Previously, the efficiency of these algorithms is compared based on the number of operations. This comparison is reasonable when these algorithms are implemented on a dedicated DSP. However, this comparison may not be suitable for general-purpose PPDSPs. The paper proposes to use three parameters, the number of data accesses, the number of communications, and the distance of communications, as new criterion for performance comparison of DCT algorithms. An algorithm-level technique is developed to estimate these parameters for DCT algorithms. The comparison results based on the parameters show that the algorithm proposed by Cho and Lee (1991) might be the best choice for a PPDSP unless it requires large overhead for communication between remote processors. In this case, the conventional row-column method with a fast 1D-DCT algorithm might be the most efficient.

关键词： Signal processing algorithms Digital signal processors Digital signal processing chips Discrete cosine transforms Digital signal processing Computer science Costs Image coding Parameter estimation Concurrent computing

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Processing noisy analog signals from microsensor arrays and VLSI imagers using stochastic binary computations

Processing noisy analog signals from microsensor arrays and ...

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Canadian conference on Electrical and Computer Engineering (CCECE)

作者： D.K. McNeill D. Zhao C. Shafai N. Chadha A. Cuhadar H.C. Card Electrical and Computer Engineering University of Manitoba Winnipeg Manitoba Canada University of Manitoba Winnipeg MB CA Dept. of Electr. & Comput. Eng. Manitoba Univ. Winnipeg Man. Canada

This paper describes the use of Bernoulli-distributed binary random variables to implement signal processing from integrated arrays of parallel microsensors and VLSI imagers. parallel digital signal processing of these signals is achieved in hardware by a combination of CMOS threshold detection of noisy raw signals, and the use of stochastic arithmetic (see Gaines, B.R., "advances in Information Systems Science", Plenum Press, vol.2, chap.2, p.37-172, 1969; Brown, B.D. and Card, H.C., IEEE Trans. Computers, vol.50, p.891-905, 2001). Hardware efficiencies include reduced power dissipation and improved error tolerance, as compared to binary radix implementations, together with the ability to trade precision against computation time using fixed hardware, reminiscent of biological computations.

关键词： Signal processing Microsensors Very large scale integration Stochastic processes Analog computers Hardware Biology computing Random variables Array signal processing Biomedical signal processing

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Challenges for parallel computing 11

Challenges for parallel computing

引用

proceedings of the 2011 conference of the Center for Advanced Studies on Collaborative Research

作者： Kit Barton Amy Wang Steven Perron Priya Unnikrishnan IBM Canada Ltd.

Over the last decade, interest in parallel programming has grown tremendously and hardware systems that contain different levels of parallelism have become mainstream. At one end of the spectrum, computer systems that contain many processing cores and are each capable of running multiple hardware threads are also becoming commonplace. It is common to find laptop and desktop systems that contain a small number (2--8) of these Shared-Memory Processor (SMP) chips. Furthermore, high-end computing systems are now able to contain hundreds of these SMP chips, resulting in machines that are capable of running more than 1000 hardware threads simultaneously. As processor speeds begin to stagnate, software developers are being forced to exploit the parallelism that is available in these systems in order to improve the performance of their *** the other end of the spectrum and as commodity hardware prices fall, it is becoming increasingly affordable to build large-scale, multi-node distributed machines. A survey of the top 10 supercomputers in the world (***) shows that the systems contain an average of 182,035 processors running at an average frequency of 2.5GHz. Since the average clock frequency of these machines is fairly low, the full potential of these systems must be exploited through efficient use of the parallelism that is provided by the thousands of processors they *** types of heterogeneous parallel computing systems have begun to emerge. These systems contain multiple types of processors - typically a powerful CPU core and some type of Graphics Processing Unit (GPU) or hardware accelerator unit. This type of heterogeneous system provides a new set of challenges for software developers in terms of how to distribute work among the different units based on their capabilities in order to maximize their utilization. Many advances in heterogeneous system design are still being realized as people continue to explore how to combine existing ha

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8th Workshop on Challenges for parallel computing 13

8th Workshop on Challenges for Parallel Computing

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proceedings of the 2013 conference of the Center for Advanced Studies on Collaborative Research

作者： Priya Unnikrishnan Kit Barton Jeremy Bradbury Reza Azimi IBM Canada Software Lab University of Ontario Institute of Technology

Over the last decade, interest in parallel programming has grown tremendously. Hardware systems that contain many different levels of parallelism have become mainstream. At one end of the spectrum, computer system that contain many processing cores, each capable of running multiple hardware threads, are becoming commonplace. It is common to find laptop and desktop systems that contain a small number of these Shared-Memory Processor (SMP) chips. Furthermore, high-end computing systems can now contain hundreds of these SMP chips, resulting in machines capable of running an incredibly large number of hardware threads simultaneously. As processor speeds begin to stagnate, software developers are being forced to exploit the parallelism that is available in these systems in order to improve the performance of their *** the other end of the spectrum, as commodity hardware prices fall it is becoming increasingly affordable to build large-scale multi-node distributed machines. A survey of the top 10 supercomputers in the world (***) shows that the systems contain an average of about 400,000 cores running at an average frequency of 2.5GHz. Since the average clock frequency of these machines is fairly low, the full potential of these systems must be exploited through efficient use of the parallelism provided by the thousands of processors they *** types of heterogeneous parallel computing system have begun to emerge. These systems contain multiple types of processors - typically a powerful CPU core and some type of Graphics Processing Unit (GPU) or hardware accelerator unit. This type of heterogeneous system provides a new set of challenges for software developers in terms of how to distribute work among the different units to maximize their utilization, based on their capabilities. Many advances in heterogeneous system design are still being realized as people continue to explore how to combine existing hardware in new and novel ways. Others sti

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7th Workshop on Challenges for parallel computing 12

7th Workshop on Challenges for Parallel Computing

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proceedings of the 2012 conference of the Center for Advanced Studies on Collaborative Research

作者： Priya Unnikrishnan Kit Barton Tom Chen IBM Canada Software Lab

Over the last decade, interest in parallel programming has grown tremendously. Hardware systems that contain many different levels of parallelism have become mainstream. At one end of the spectrum, computer system that contain many processing cores, each capable of running multiple hardware threads, are becoming commonplace. It is common to find laptop and desktop systems that contain a small number (2--8) of these Shared-Memory Processor (SMP) chips. Furthermore, high-end computing systems can now contain hundreds of these SMP chips, resulting in machines capable of running more than 1000 hardware threads simultaneously. As processor speed begins to stagnate, software developers are being forced to exploit the parallelism that is available in these systems in order to improve the performance of their *** the other end of the spectrum, as commodity hardware prices fall, it is becoming increasingly affordable to build large-scale multi-node distributed machines. A survey of the top 10 supercomputers in the world (***) shows that the systems contain an average of about 400,000 cores running at an average frequency of 2.5GHz. Since the average clock frequency of these machines is fairly low, the full potential of these systems must be exploited through efficient use of the parallelism provided by the thousands of processors they *** types of heterogeneous parallel computing system have begun to emerge. These systems contain multiple types of processors - typically a powerful CPU core and some type of Graphics Processing Unit (GPU) or hardware accelerator unit. This type of heterogeneous system provides a new set of challenges for software developers in terms of how to distribute work among the different units to maximize their utilization, based on their capabilities. Many advances in heterogeneous system design are still being realized as people continue to explore how to combine existing hardware in new and novel ways. Others still are

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Load balancing and communication optimization for parallel adaptive finite element methods

Load balancing and communication optimization for parallel a...

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Computer Science Society (SCCC) International conference Chilean FLAGGED

作者： J.E. Flaherty R.M. Loy P.C. Scully M.S. Shephard B.K. Szymanski J.D. Teresco L.H. Ziantz Computer Science Department and Scientific Computation Research Center Rensselaer Polytechnic Institute Troy NY USA

The paper describes predictive load balancing schemes designed for use with parallel adaptive finite element methods. We provide an overview of data structures suitable for distributed storage of finite element mesh data as well as software designed for mesh adaptation and load balancing. During the course of a parallel computation, processor load imbalances are introduced at adaptive enrichment steps. The predictive load balancing methods described here use a priori estimates of work load for adaptive refinement and subsequent computation to improve enrichment efficiency and reduce total balancing time. An analysis code developed with these components for solving compressible flow problems is used to obtain predictive load balancing results on an IBM SP2 computer. Our test problem involves the transient solution of the three dimensional Euler equations of compressible flow inside a perforated shock tube. We also present a message passing library extension in development which allows for automated packing of messages to improve communication efficiency.

关键词： Load management Finite element methods Data structures Software design Concurrent computing Load flow analysis Testing Equations Electric shock Message passing

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