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Dynamic scheduling of parallelizable tasks and resource reclaiming in real-time multiprocessor systems

Dynamic scheduling of parallelizable tasks and resource recl...

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International conference on High Performance Computing

作者： G. Manimaran C. Siva Ram Murthy Department of Computer Science and Engineering Indian Institute of Technology Chennai India

Many time critical applications require predictable performance and tasks in these applications have deadlines to be met despite the presence of faults. We propose a new dynamic non preemptive scheduling algorithm for a relatively new task model called parallelizable task model where real time tasks can be executed concurrently on multiple processors. We use this parallelism in tasks to meet their deadlines and thus obtain better processor utilization compared to nonparallelizable task scheduling algorithms. We assume that tasks are aperiodic. Further, each task is characterized by its deadline, resource requirements, and worst case computation time on p processors, where p is the degree of task parallelization. To study the effectiveness of our algorithm, we have conducted extensive simulation studies and compared its performance with the myopic scheduling algorithm (K. Ramamritham et al., 1990). We found that the success ratio offered by our algorithm is always higher than the myopic algorithm for a wide variety of task parameters. Also, we propose a resource reclaiming algorithm to reclaim resources from parallelizable real time tasks when their actual computation times are less than their worst case computation times. Our parallelizable task scheduling together with its associated reclaiming offers the best guarantee ratio compared to the other algorithmic combinations.

关键词： Dynamic scheduling Processor scheduling Job shop scheduling Scheduling algorithm Concurrent computing Heuristic algorithms Real time systems Multiprocessing systems Application software Computer science

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An efficient multi-way algorithm for balanced partitioning of VLSI circuits

An efficient multi-way algorithm for balanced partitioning o...

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IEEE International conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： X. Tan J. Tong P. Tan N. Park F. Lombardi Department of Electronic Engineering Fudan University Shanghai China Department of Computer Science Texas A and M University College Station TX USA

This paper presents an efficient algorithm for multi-way balanced partitioning of VLSI circuits. The proposed algorithm is still based on the widely used net-cut model, but its novelty is the potential gain function into the net-cut cost function to relax the single-cell-move constraint (as commonly encountered in the Kernighan-Lin algorithm) for balanced partitioning. This feature permits to move a group of cells (referred to as a Multi-Cell-Move strategy) for partitioning a circuit, while reducing its sensitivity to size constraint. The new multi-way partitioning algorithm is fully analyzed; expressions for the potential gain function (with respect to the multi-move operation) and the cost (for the min-cut objective function) are presented. The time complexity of the proposed partitioning algorithm is O(P/spl times/k/sup 2/ log/sub 2/ (k)), where k is the number of blocks and P is the number of pins. simulation results are presented and a remarkable improvement is achieved compared with existing algorithms, such as the k-Dual Part algorithm.

关键词： Partitioning algorithms Very large scale integration Circuits Cost function Algorithm design and analysis Pins

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On the actual use of inheritance and interface in java projects: evolution and implications 17

On the actual use of inheritance and interface in Java proje...

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proceedings of the 27th Annual International conference on Computer science and Software engineering

作者： Carlos E. C. Dantas Marcelo de A. Maia Federal University of Uberlândia MG - Brazil

Background: Inheritance is one of the main features in the object-oriented paradigm (OOP). Nonetheless, previous work recommend carefully using it, suggesting alternatives such as the adoption of composition with implementation of interfaces. Despite of being a well-studied theme, there is still little knowledge if such recommendations have been widely adopted by developers in general. Aims: This work aims at evaluating how the inheritance and composition with interfaces have been used in java, comparing new projects with older ones (transversal), and also the different releases of the same projects (longitudinal). Method: A total of 1, 656 open-source projects built between 1997 and 2013, hosted in the repositories GitHub and SourceForge, were analyzed. The likelihood of more recent projects using inheritance and interfaces differently from older ones was analyzed considering indicators, such as, the prevalence of corrective changes, instanceof operations, and code smells. Regression analysis, chi-squared test of proportions and descriptive statistics were used to analyze the data. In addition, a thematic analysis based method was used to verify how often and why inheritance and interface are added or removed from classes. Results: We observed that developers still use inheritance primarily for code reuse, motivated by the need to avoid duplicity of source code. In newer projects, classes in inheritance had fewer corrective changes and subclasses had fewer use of the instance of operator. However, as they evolve, classes in inheritance tend to become complex as changes occur. Classes implementing interfaces have shown little relation to the interfaces, and there is indication that interfaces are still underutilized. Conclusion: These results show there is still some lack of knowledge about the use of recommended object-oriented practices, suggesting the need of training developers on how to design better classes.

关键词： interfaces inheritance cohesion code smells GitHub sourceforge

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A model and design of a fully distributed computing environment for virtual reality

A model and design of a fully distributed computing environm...

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IEEE International conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Jiung-Yao Huang Chao-Tsong Fang-Tson Shuenn-Jyi Wang Wei-Chyuan Wang Multimedia and Virtual Reality Laboratory Institute of Computer Science and Information Engineering Tamkang University Tamsui Taiwan Avionics Development Center Institute for Information Industry Taipei Taiwan

ISBN: (纸本)0818680733

With the evolution of computing technologies, both PCs and workstations have increased computing power with less cost in the recent years. This paper presents a model and design of a fully distributed virtual reality system, called Multiple User Distributed simulation (MUDS) system, over a network of low-end computers. MUDS system is designed to provide a virtual environment for both a single user and multiple participants over a fully distributed environment. However, only the method and architecture of building a single user distributed virtual environment is presented in this paper. MUDS system adapts and modifies the concepts from High Level Architecture, which is designed by DoD of US to provide interoperability among distributed simulators. Compared to the other existing distributed systems, MUDS system provides a transparent interface among distributed tasks. The prototype of MUDS system has been successfully built in Institute of Computer science and Information engineering, Tamkang University. An experiment of using MUDS system along with the experimental result will also be fully discussed in the paper.

关键词： Distributed computing Multiuser detection Power system modeling Computational modeling Virtual environment Computer architecture Personal communication networks Workstations Costs Virtual reality

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A visual computing environment for very large scale biomolecular modeling

A visual computing environment for very large scale biomolec...

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International conference on Application Specific Systems (ASAP), Architectures and Processors

作者： M. Zeller J.C. Phillips A. Dalke W. Humphrey K. Schulten R. Sharma T.S. Huang V.I. Pavlovic Y. Zhao Z. Lo S. Chu Backman Institute for Advanced Science and Technology University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

Knowledge of the complex molecular structures of living cells is being accumulated at a tremendous rate. Key technologies enabling this success have been, high performance computing and powerful molecular graphics applications, but the technology is beginning to seriously lag behind challenges posed by the size and number of new structures and by the emerging opportunities in drug design and genetic engineering. A visual computing environment is being developed which permits interactive modeling of biopolymers by linking a 3D molecular graphics program with an efficient molecular dynamics simulation program executed on remote high-performance parallel computers. The system will be ideally suited for distributed computing environments, by utilizing both local 3D graphics facilities and the peak capacity of high-performance computers for the purpose of interactive biomolecular modeling. To create an interactive 3D environment three input methods will be explored: (1) a six degree of freedom "mouse" for controlling the space shared by the model and the user; (2) voice commands monitored through a microphone and recognized by a speech recognition interface; (3) hand gestures, detected through cameras and interpreted using computer vision techniques. Controlling 3D graphics connected to real time simulations and the use of voice with suitable language semantics, as well as hand gestures, promise great benefits for many types of problem solving environments. Our focus on structural biology takes advantage of existing sophisticated software, provides concrete objectives, defines a well-posed domain of tasks and offers a well-developed vocabulary for spoken communication.

关键词： Large-scale systems Computer graphics Pharmaceutical technology Concurrent computing Computational modeling Distributed computing Speech recognition High performance computing Drugs Genetic engineering

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Smooth particle applied mechanics implemented in the clustered machines with PVM

Smooth particle applied mechanics implemented in the cluster...

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International conference on High Performance Computing in the Asia-Pacific Region

作者： Oyeon Kum Ki-Bok Hahn Sungho Kim Jang-Hyuk Kwon Agency for Defence Development Taejon South Korea Department of Aerospace Engineering Korea Advanced Institute of Science and Technology Taejon South Korea

Smooth particle applied mechanics (SPAM) solves the continuum equations for the time development of coordinates, velocities, and specific energies p,v,e of a moving grid of "smoothed particles". By eliminating the ordered grid, the smooth particle method resembles the method used in atomistic and molecular dynamics. Consequently, there are no usual grid-based distortional instabilities which plague simulation with large deformation. Their implementation on parallel computers is also straightforward. Complex hydrodynamic problems-shock propagation, Richtmyer-Meshkov instability, and Rayleigh-Benard instability are solved with smooth particle applied mechanics using clustered workstations and Cray C90 with a portable software system of parallel virtual machine (PVM). Multiple informations and multiple data (MIMD) and single program and multiple data (SPMD) methods provide good algorithms for SPAM.

关键词： Unsolicited electronic mail Equations Computational modeling Deformable models Concurrent computing Hydrodynamics Workstations Software systems Virtual machining Clustering algorithms

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Advances in agile manufacturing

Advances in agile manufacturing

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IEEE International conference on Robotics and Automation (ICRA)

作者： F.L. Merat N.A. Barendt R.D. Quinn G.C. Causey W.S. Newman V.B. Velasco A. Podgurski Y. Kim G. Ozsoyoglu J.-Y. Jo Center for Automation and Intelligent Systems Research Department of electrical Engineeisng and Applied Physics Case Western Reserve University Cleveland OH USA Center for Automation and Intelligent Systems Research Department of Mechanical and Aerospace Engineering Case Western Reserve University Cleveland OH USA Center for Automation and Intelligent Systems Research Department of Computer Engineering and Science Case Western Reserve University Cleveland OH USA

An agile workcell has been developed for light mechanical assembly in collaboration with industrial sponsors. The workcell includes multiple Adept robots, a Bosch conveyor system, multiple flexible parts feeders at each robot's workstation, CCD cameras for parts feeding and hardware registration, and a dual VMEbus control system. Our flexible pairs feeder design uses multiple conveyors to singulate the parts and machine vision to locate them. Specialized hardware is encapsulated on modular grippers and modular worktables which can be quickly interchanged for assembly of different products. Object-oriented software (C++) running under VxWorks, a real-time operating system, is used for workcell control. An agile software architecture was developed for rapid introduction of new assemblies through code re-use. A simulation of the workcell was developed so that controller software could be written and tested off-line, enabling the rapid introduction of new products.

关键词： Agile manufacturing Robotic assembly Service robots Hardware Control systems Collaborative work Electrical equipment industry Manufacturing industries Workstations Charge coupled devices

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On measuring the performance of adaptive wormhole routing

On measuring the performance of adaptive wormhole routing

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International conference on High Performance Computing

作者： L. Schwiebert D.N. Jayasimha Department of Electrical & Computer Engineering Wayne State University Detroit MI USA Intel Corporation Santa Clara CA USA

Adaptive routing is widely regarded as a promising approach to improving interconnection network performance. Many designers of adaptive routing algorithms have used synthetic communication patterns, such as uniform and transpose traffic, to compare the performance of various adaptive routing algorithms with each other and with oblivious routing. These comparisons have shown that the average message latency is usually lower with adaptive routing. On the other hand, when a parallel program is executed on a multiprocessor the goal is to reduce the total execution time. We explain why improving the average message latency of a routing algorithm does not necessarily lead to a lower execution time for real applications. We support this observation by reporting simulation results for both adaptive and oblivious routing using communication derived from real applications. Specifically, we report the performance of various routing algorithms for directed acyclic graphs (DAGs) derived from the Cholesky factorization of sparse matrices. Our results show that there is little correlation between average message latency and the total execution time of a parallel program. Hence, average message latency does not seem to be a useful measure of the performance of a routing algorithm. This strongly suggests that current comparisons of routing algorithms do not provide a reliable indication of the performance improvements to be realized by executing programs on a multiprocessor with such a routing algorithm. We interpret these results and suggest several alternatives for further research.

关键词： Routing Delay Buffer storage Hardware Multiprocessor interconnection networks Algorithm design and analysis Sparse matrices Information science Large-scale systems

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A fast optimal slot reuse scheme for CRMA high speed networks

A fast optimal slot reuse scheme for CRMA high speed network...

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conference on Local Computer Networks (LCN)

作者： Pi-Rong Sheu Charng-Maw Lin Department of Electrical Engineering National Yunlin University of Science and Technology Taiwan

ISBN: (纸本)0818681411

Cyclic-reservation multiple-access (CRMA) is an access scheme for high-speed local and metropolitan area networks based on folded-bus or dual-bus configurations. CRMA provides high throughput and fairness independent of the network speed or distance. In CRMA, the headend generates reserve commands periodically. Each station may reserve a number of empty slots in each reserve command if necessary. Corresponding to every reserve command, the headend generates a cycle of length equal to the total number of empty slots reserved. Every cycle is used to serve the reservations made on its corresponding reserve command. Generally, a longer cycle length means a longer access delay and a lower throughput. Therefore, it is desirable to develop a scheme such that the cycle length is the shortest. The authors study the problem of reducing the total number of empty slots generated within every cycle. However, it has been shown that the problem is NP-complete under the constraint that all the empty slots used by a station in a cycle are required to be consecutive. They release the slot-contiguity constraint and propose a fast optimal slot reuse scheme with low time complexity O(M/sup 2/), where M is the number of stations. To evaluate the effectiveness of the slot reuse scheme, a large number of computer simulations are performed. They compare the slot reuse scheme with the original CRMA in terms of the following three important performance measurements: average cycle length, average throughput, and average MAC delay.

关键词： High-speed networks Throughput Metropolitan area networks Delay Computer simulation Performance evaluation Measurement Media Access Protocol Councils Costs

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Compact signed-digit adder using multiple-valued logic

Compact signed-digit adder using multiple-valued logic

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conference on Advanced Research in VLSI

作者： A.F. Gonzalez P. Mazumder Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA

As minimum feature sizes shrink and the number of transistors integrated in a single chip grow, interconnect complexity is one of the most important issues to be solved in future VLSI chips. The use of multivalued logic is one way to effectively solve this problem because multiple-valued signals convey more information than binary signals and thus, require a lower number of interconnecting wires to achieve similar bandwidths. This paper describes a new signed-digit adder design, which uses multiple-valued logic. The circuit is composed of resonant-tunneling diodes (RTDs) and MOS transistors. The negative differential-resistance (NDR) characteristics of RTDs help to achieve very compact circuits for implementing the multiple-valued functions found in signed-digit adders, MOS transistors are useful for implementing current-mode logic, in which addition of two or more signals is performed by simple wire interconnection. Since a redundant arithmetic is being used the selected transfer functions allow the proposed circuit to perform addition where no ripple-carry effect is present. The design was verified using circuit simulation. To demonstrate the validity of the principles being used, a modified prototype of the circuit was built. In the prototype, a standard 2-micron CMOS process was used to fabricate the MOS-based circuitry while RTDs were connected externally. Even though no fabrication processes which integrate RTDs and MOS devices are currently available, there are efforts on the development of such technologies so that the advantages of these devices can be combined.

关键词： Adders Integrated circuit interconnections MOSFETs Prototypes Transistors Very large scale integration Multivalued logic Wires Bandwidth Logic design

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