A new technique for representing and decoding of non-linear block codes has been investigated based on the tree-trellis construction method. Such a technique is applied to the EFMPlus recording code used in the DVD. B...
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A new technique for representing and decoding of non-linear block codes has been investigated based on the tree-trellis construction method. Such a technique is applied to the EFMPlus recording code used in the DVD. By employing the tree-trellis construction technique, a reduction in the overall complexity of the decoding process can be achieved. Simulation test results have also shown that a performance improvement has been attained for the new technique when compared to the conventional decoding method.
The DAP Gamma II is a single instruction multiple data (SIMD) computer of either 1024 or 4096 processors which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languag...
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The DAP Gamma II is a single instruction multiple data (SIMD) computer of either 1024 or 4096 processors which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languages (Fortran Plus and C++), low level languages, and library functions. For easy development and signal applications, there is also a development system based on Khoros. Various high-speed I/O interfaces are supported, however, the DAP contains a sufficiently large memory to allow sequences of whole-image operations to be performed without any intermediate I/O.
BRIGHT RF integrated circuits (IC) are highly integrated radio receivers designed for the Global Systems for Mobile (GSM) communication digital cellular system. The BRIGHT devices are the result of a four-year collabo...
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BRIGHT RF integrated circuits (IC) are highly integrated radio receivers designed for the Global Systems for Mobile (GSM) communication digital cellular system. The BRIGHT devices are the result of a four-year collaboration between the Technology Partnership and Hitachi which was brought together TTP Communications' GSM system expertise and Hitachi's world class linear IC technology. A dual band device based on the earlier single band 900 MHz and 1800 MHz devices is discussed.
Quantisation is employed in MPEG video coders as a video rate control scheme to regulate the data rate of compressed video bit stream entering the transmission buffer. For constant bit rate applications, the quantiser...
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Quantisation is employed in MPEG video coders as a video rate control scheme to regulate the data rate of compressed video bit stream entering the transmission buffer. For constant bit rate applications, the quantiser has a crucial effect on video data rate and video quality. It has been a challenging task to optimise the quantiser step size for both bit rate and quality since they are mutually exclusive parameters, as defined by rate-distortion theory. The quantiser step size is generally determined by a linear relationship with respect to the buffer occupancy. Two nonlinear quantiser control functions are investigated, sigmoidal and unimodal, which achieve superior video rate control performance while maintaining similar video quality to the linear one. These two functions are analysed in the framework of rate-distortion theory. Their performance for video rate fluctuation has also been analysed. Encoding results for the two functions are compared to the MPEG2 TM5 evaluation model.
A new technique for modelling the entire analogue front-end of an RF IC for fast simulation and analysis in a DSP design environment is described. The designer's objective is to see if an existing analogue front-e...
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A new technique for modelling the entire analogue front-end of an RF IC for fast simulation and analysis in a DSP design environment is described. The designer's objective is to see if an existing analogue front-end circuit design will work in the target end-to-end system before the RF IC is fabricated. Accurate full system simulation might save the need for chip redesign, mask generation and refabrication. A wireless receiver's analogue front-end circuitry introduces varying levels of distortion dependent on carrier bias. To simulate the RF front-end in a system simulation, time-domain based behavioural models, K-models, are used to represent the receiver's non-linear effects. With SpectreRF's Periodic AC and Periodic Noise analyses the receiver's non-linear frequency translating and noise effects are accurately characterized. A scripting language called OCEANTM is used to write an extraction program to run SpectreRFTM simulations and save the necessary base-band to base-band frequency response and Power Spectral Density data files. K-models reside in the signalprocessing Work System (SPWTM) as block diagram symbols. The K-model uses the SpectreRFTM data from the extraction simulation to define its non-linear performance. Full end to end system simulations are then analyzed within SPWTM. The K-model behavioural simulation approach is found to be extremely fast when compared with full circuit transistor level simulation techniques.
A comparison between the Texas Instruments TMS320C80 programmable digital signal processor and a Xilinx field programmable gate array (FPGA) is presented for implementing a multiscale convolution (MSC) algorithm. The ...
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A comparison between the Texas Instruments TMS320C80 programmable digital signal processor and a Xilinx field programmable gate array (FPGA) is presented for implementing a multiscale convolution (MSC) algorithm. The merits and the disadvantages of each implementation are discussed. The MSC algorithm is useful in imageprocessing because it allows the detection of targets within images, where the scale of the target is unknown.
A non-intrusive method for monitoring salmon stock has been developed which includes the use of two matched monochrome CCD cameras. Stereo image sequences are grabbed and digitized. The images are used to calculate va...
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A non-intrusive method for monitoring salmon stock has been developed which includes the use of two matched monochrome CCD cameras. Stereo image sequences are grabbed and digitized. The images are used to calculate various measurements from the fish, which are then used to estimate its mass. Methods for estimating the fish mass have been investigated. An image analysis algorithm for locating salmon from an underwater image has been developed and more advanced techniques are under development.
The real time hardware architecture of a deterministic video echo canceller (deghoster) system is presented. The deghoster is capable of calculating all the multipath channel distortion characteristics from terrestria...
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The real time hardware architecture of a deterministic video echo canceller (deghoster) system is presented. The deghoster is capable of calculating all the multipath channel distortion characteristics from terrestrial and cable television in one single pass while performing real time video in-line ghost cancellation. The results from the actual system are also presented in this paper.
Presents a brief discussion of the need for and evolution to nonlinear and nonstationary signalprocessing. Applications where these are useful are mentioned.
Presents a brief discussion of the need for and evolution to nonlinear and nonstationary signalprocessing. Applications where these are useful are mentioned.
A 64-bit computer processor architecture capable of performing a maximum of eight instructions per cycle, but with an instruction word much shorter, is presented. These performances are obtained through the addressing...
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A 64-bit computer processor architecture capable of performing a maximum of eight instructions per cycle, but with an instruction word much shorter, is presented. These performances are obtained through the addressing of 128 registers storing the most frequently executed instructions. It is shown that the drawback of the instruction register file (IRF) initialization is not significant for digital signalprocessing applications. In combination with a high-speed external memory, this operation is even much faster than the instruction cache initialization necessary in every traditional very long instruction word (VLIW) architecture. For this reason, indirect reduced instruction set computing represents a solution for extending the application of VLIW.
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