the proceedings contains 25 papers from the 1998 acm/sigdainternationalsymposium on fieldprogrammablegatearrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA sys...
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the proceedings contains 25 papers from the 1998 acm/sigdainternationalsymposium on fieldprogrammablegatearrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA systems & other reprogrammable architectures;partitioning and floor planning for FPGAs;fault detection and fault tolerance for FPGAs;fast computer aided design (CAD) tools for FPGAs;time multiplexed FPGAs;FPGAs with embedded memory;and programmable architectures with special features.
the proceedings contain 34 papers. the topics discussed include: emerging application domains - research challenges and opportunities for FPGAs;towards automated ECOs in FPGAs;clock power reduction for Virtex-5 FPGAs;...
ISBN:
(纸本)9781605584102
the proceedings contain 34 papers. the topics discussed include: emerging application domains - research challenges and opportunities for FPGAs;towards automated ECOs in FPGAs;clock power reduction for Virtex-5 FPGAs;choose-your-own-adventure routing: lightweight load-time defect avoidance;towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs;a comparison of via-programmablegate array logic cell circuits;a comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation;a high-performance FPGA architecture for restricted Boltzmann machines;FPGA-based front-end electronics for positron emission tomography;FPGA-based face detection system using Haar classifiers;a 17ps time-to-digital converter implemented in 65nm FPGA technology;and FPGA technology mapping with encoded libraries and staged priority cuts.
the proceedings contain 34 papers. the topics discussed include: FPGA prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on FPGAs;energy efficient s...
ISBN:
(纸本)9781605589114
the proceedings contain 34 papers. the topics discussed include: FPGA prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on FPGAs;energy efficient sensor node implementations;high throughput and large capacity pipelined dynamic search tree on FPGA;FPMR: MapReduce framework on FPGA: a case study of RankBoost acceleration;Axel: a heterogeneous cluster with FPGAs and GPUs;building a faster Boolean matcher using bloom filter;scalable network virtualization using FPGAs;maximizing area-constrained partial fault tolerance in reconfigurable logic;FPGA based chip emulation system for test development and verification of analog and mixed signal circuits;a semi-automatic Toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning;and a dependency graph based methodology for parallelizing HLL applications on FPGA.
the proceedings contain 37 papers. the topics discussed include: comparing FPGA vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: autom...
ISBN:
(纸本)9781450305549
the proceedings contain 37 papers. the topics discussed include: comparing FPGA vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: automatic memory and cache management for reconfigurable logic;NETTM: faster and easier synchronization for soft multicores via transactional memory;LegUp: high-level synthesis for FPGA-based processor/accelerator systems;automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs;Torc: towards an open-source tool flow;FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting;a platform for high level synthesis of memory-intensive image processing algorithms;energy-efficient specialization of functional units in a coarse-grained reconfigurable array;and DEEP: an iterative FPGA-based many-core emulation system for chip verification and architecture research.
the proceedings contain 22 papers. the topics discussed include: embedded floating-point units in FPGAs;measuring the gap between FPGAs and ASICs;optimality study of logic synthesis for LUT-based FPGAs;improvements to...
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ISBN:
(纸本)1595932925
the proceedings contain 22 papers. the topics discussed include: embedded floating-point units in FPGAs;measuring the gap between FPGAs and ASICs;optimality study of logic synthesis for LUT-based FPGAs;improvements to technology mapping for LUT-based FPGAs;improving performance and robustness of domain-specific CPLDs;design, implementation, and verification of active cache emulator (ACE);modeling and data-dependent performance of pattern-matching architectures;yield enhancements of design-specific FPGAs;FGPA clock network architecture: flexibility vs. area and power;a reconfigurable hardware based embedded scheduler for buffered crossbar switches;and combining module selection and resource sharing for efficient FPGA pipeline synthesis.
the proceedings contain 24 papers. the topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for FPGAs on commodity hardware;enforcing long-path timing closure for...
ISBN:
(纸本)9781595939340
the proceedings contain 24 papers. the topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for FPGAs on commodity hardware;enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals;mapping for better than worst-case delays in LUT-based FPGA designs;a complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs;efficient ASIP design for configurable processors with fine-grained resource sharing;pattern-based behavior synthesis for FPGA resource reduction;modeling routing demand for early-stage FPGA architecture development;and trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emission...
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ISBN:
(纸本)9781450305549
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an FPGA chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in FPGAs. Given that FPGAs are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from FPGAs into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.
Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with t...
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ISBN:
(纸本)9781450305549
Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale withthe number of cores in many cases. In our work, we present our FPGA-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RIM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from boththe algorithmic and architectural perspectives, our FPGA-based solution manages to remove the memory constraints and provide a high performance that can scale well withthe amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 FPGAs, and 8x speedup on two Virtex-6 FPGAs. Our projection demonstrates that the performance will continue to scale withthe future increase of FPGA capacities.
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