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检索条件"任意字段=Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays"

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Technology mapping for FPGAs with embedded memory blocks 98

Technology mapping for FPGAs with embedded memory blocks

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cong, Jason Xu, Songjie Univ of California Los Angeles CA United States

ISBN: (纸本)9780897919784

Modern field programmable gate arrays (FPGAs) provide embedded memory blocks (EMBs) to be used as on-chip memories. In this paper, we explore the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. We propose a general technology mapping problem for FPGAs with EMBs for area and delay minimization and develop an efficient algorithm based on the concepts of Maximum Fanout Free Cone (MFFC) and Maximum Fanout Free Subgraph (MFFS), named EMB_Pack, which minimizes the area after or before technology mapping by using EMBs while maintaining the circuit delay. We have tested EMB_Pack on MCNC benchmarks on Altera's FLEX10K device family. the experimental results show that compared with the original mapped circuits generated from CutMap without using EMBs, EMB_Pack as postprocessing can further reduce up to 10% of the area on the mapped circuits while maintaining the layout delay by making efficient use of available EMB resources. Compared with CutMap-e without using EMBs, EMB_Pack as pre-mapping processing followed by CutMap-e can reduce 6% of the area while maintaining the circuit optimal delay.

关键词： field programmable gate arrays

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SmartOpt: An industrial strength framework logic synthesis

SmartOpt: An industrial strength framework logic synthesis

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jang, Stephen Wu, Dennis Jarvin, Mark Chan, Billy Chung, Kevin Mishchenko, Alan Brayton, Robert Xilinx Inc United States University of California Berkeley United States

ISBN: (纸本)9781605584102

In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial FPGAs. this paper presents a framework (SmartOpt) for mapping complex FPGA architectures to a simple netlist model, which can be supported by academic tools. SmartOpt was applied to leverage the algorithms implemented in the ABC package and to study their relative contributions. this work is integrated into the Xilinx ISE 11.1 software flow for FPGAs and shows significant improvements in both the LUT count and performance of large industrial circuits described in HDL. Xilinx Synthesis Technology (XST) reference flow was compared experimentally against the same flow augmented by SmartOpt. When applied to a set of 20 large industrial Virtex-5 benchmarks ranging from 17K to 69K 6- LUTs, the augmented flow produced 8.3% fewer LUTs and led to 2.1% higher operating frequency while keeping runtimes reasonable. With dual-LUT-merging, the LUT count is reduced by 22.7%, while increasing the operating frequency only by 0.7%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation 98

Boolean matching for complex PLBs in LUT-based FPGAs with ap...

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cong, Jason Hwang, Yean-Yow Univ of California Los Angeles CA United States

ISBN: (纸本)9780897919784

In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but also can implement some wide functions of more than K variables. We apply previous and develop new functional decomposition methods to match wide functions to PLBs. We can determine exactly whether a given wide function can be implemented with a XC4000 CLB or other three PLB architectures (including the XC5200 CLB). We evaluate functional capabilities of the four PLB architectures on implementing wide functions in MCNC benchmarks. Experiments show that the XC4000 CLB can be used to implement up to 98% of 6-cuts and 88% of 7-cuts in MCNC benchmarks, while two of the other three PLB architectures have a smaller cost in terms of logic capability per silicon area. Our results are useful for designing future logic unit architectures in LUT based FPGAs.

关键词： field programmable gate arrays

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Towards automated ECOs in FPGAs

Towards automated ECOs in FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Andrew Brown, Stephen Zhu, Jianwen Safarpour, Sean Electrical and ComputerEngineering University of Toronto Canada Toronto Technology Center Altera Corporation Canada

ISBN: (纸本)9781605584102

During the FPGA design flow, engineering change orders (ECOs) have become an essential methodology to apply late-stage specification changes and bug fixes. ECOs are beneficial since they are applied directly to a place-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which has an unpredictable impact on the design's final correctness and end costs. As a solution, we introduce an automated method to tackle the ECO problem. Specifically, we introduce a resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design;thereby removing the inefficient manual effort required by a designer. Our technique is robust enough to handle a wide range of changes. Furthermore, our technique can successfully make late-stage functional changes while minimally perturbing the place-and-routed netlist: something that is necessary for ECOs. When applied to several benchmarks on Altera's Stratix architecture, we show that our approach can automatically apply ECOs in over 80% of the cases presented. Furthermore, our technique does this with a minimal impact to the circuit performance where on average over 90% of the placement and routing wires remain unchanged. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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CMOS continuous-time field programmable analog array

CMOS continuous-time field programmable analog array

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proceedings of the 1997 acm 5th international symposium on field-programmable gate arrays, FPGA

作者： Looby, C.A. Lyden, C. Univ Coll Cork Ireland

A circuit design for a field programmable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to implement the user's chosen circuit. the configurable connections are realized by CMOS switches and a new innovation is that these are either buffered or nulled to cancel parasitic error. the function blocks are Op-Amps combined with passive networks which allow programmable transfer functions with accuracy insensitive to variations in process parameters and environment. the intended application area is the rapid development of analog circuits which are presently prototyped by PCBs stuffed with Op-Amp and passive components. the concept has been demonstrated on a CMOS IC and the resulting performance shows the feasibility of this approach to general purpose FPAA technology.

关键词： CMOS integrated circuits

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A high-performance FPGA architecture for restricted machines

A high-performance FPGA architecture for restricted machines

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ly, Daniel L. Chow, Paul Department of Electrical and Computer Engineering University of Toronto Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781605584102

ef>Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of is due to the fact that neural networks are usually as software running on general-purpose processors. to implement a neural network in software typically O(n2) problems - as a result, neural networks unable to provide the performance and scalability required non-academic settings. this paper, we investigate how FPGAs can be used take advantage of the inherent parallelism in neural networks provide a better implementation in terms of scalability performance. We will focus on the Restricted machine, a popular type of neural network, because architecture is particularly well-suited to hardware . the proposed, multi-purpose hardware framework designed to reduce the O(n2) problem into an O(n) implementation only requiring O(n) resources. the framework tested on a Xilinx Virtex II-Pro XC2VP70 FPGA at 100MHz. the resources support a Restricted machine of 128 x 128 nodes, which results in computational speed of 1.02 billion connection-updatesper- and a speed-up of 35 fold over an optimized C program running on a 2.8GHz Intel processor. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Large-scale wire-speed packet classification on FPGAs

Large-scale wire-speed packet classification on FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jiang, Weirong Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)9781605584102

Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Although a plethora of research has been done in this area, wire-speed packet classification while supporting large rule sets remains difficult. this paper exploits the features provided by current FPGAs and proposes a decision-tree-based, two-dimensional dual-pipeline architecture for multi-field packet classification. To fit the current largest rule set in the on-chip memory of the FPGA device, we propose several optimization techniques for the stateof- the-art decision-tree-based algorithm, so that the memory requirement is almost linear with the number of rules. Specialized logic is developed to support varying number of branches at each decision tree node. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization. Since our architecture is linear and memory based, on-the-fly update without disturbing the ongoing operations is feasible. the implementation results show that our architecture can store 10K real-life rules in on-chip memory of a single Xilinx Virtex-5 FPGA, and sustain 80 Gbps (i.e. 2 OC-768 rate) throughput for minimum size (40 bytes) packets. To the best of our knowledge, this work is the first FPGA-based packet classification engine that achieves wire-speed throughput while supporting 10K unique rules. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Fast module mapping and placement for datapaths in FPGAs 98

Fast module mapping and placement for datapaths in FPGAs

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Callahan, Timothy J. Chong, Philip DeHon, Andre Wawrzynek, John Univ of California at Berkeley Berkeley CA United States

ISBN: (纸本)9780897919784

By tailoring a compiler tree-parsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure;this allows exploitation of specialized datapath features in FPGAs, retains regularity, and also results in a smaller problem size. To further achieve high mapping speed, we formulate the problem as tree covering and solve it efficiently with a linear-time dynamic programming algorithm. In a novel extension to the tree-covering algorithm, we perform module placement simultaneously with the mapping, still in linear time. Integrating placement has the potential to increase the quality of the result since we can optimize total delay including routing delays. To our knowledge this is the first effort to leverage a grammar-based tree covering tool for datapath module mapping. Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity.

关键词： field programmable gate arrays

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Scalable don't-care-based logic optimization and resynthesis

Scalable don't-care-based logic optimization and resynthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Mishchenko, Alan Brayton, Robert Jiang, Jie-Hong Roland Jang, Stephen Department of EECS University of California Berkeley United States Department of EE National Taiwan University Taiwan Xilinx Inc. San Jose CA United States

ISBN: (纸本)9781605584102

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. the proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. the approach uses don't cares computed for a window surrounding a node and can take into account external don't cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. this representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. the longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT count and logic level is reduced by 11.8% and 16.5%, respectively. Experimental results on 6-input LUT networks after high-effort synthesis show substantial reductions in area and delay. the longest runtime is about 30 minutes. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Implementation of delay line with fine range discretization for radar target simulations 19

Implementation of delay line with fine range discretization ...

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19th international Radar symposium (IRS)

作者： Steins, Manuel Diewald, Andreas R. Univ Appl Sci Lab Radar Technol & Opt Syst D-54293 Trier Germany

In this paper the authors describes the realization of an FPGA based digital delay line for use in radar target simulators. Range resolutions up to the micrometer range are produced with a fine discretization FIR filter.

ISBN: (纸本)9783736995451

关键词： Radar Finite impulse response filters Delay lines field programmable gate arrays Radar antennas Doppler effect Baseband

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